公开(公告)号：US20240184615A1

公开(公告)日：2024-06-06

申请号：US18525312

申请日：2023-11-30

Applicant: Acer Incorporated

Inventor： Sheng-Hsin FAN ,  Chao-Kuang YANG ,  Liang-Chi CHEN

IPC: G06F9/46 ,  G06F9/54 ,  H04N23/90

CPC classification number: G06F9/462 ,  G06F9/542 ,  H04N23/90

Abstract: An electronic device capable of performing multi-camera intelligent switching and a multi-camera intelligent switching method thereof are provided. The electronic device includes a plurality of camera device media foundation transform (camara DMFT) units, an integrated DMFT unit and a mix camera agent. Each of the camera DMFT units is connected to one of a plurality of cameras. The integrated DMFT unit is serially connected to one of the camera DMFT units. The mix camera agent is connected to the cameras. The mix camera agent is used for obtaining a switching notification signal. The integrated DMFT unit switches a serial path between the integrated DMFT unit and one of the camera DMFT units according to the switching notification signal.

公开(公告)号：US20180293073A1

公开(公告)日：2018-10-11

申请号：US15944655

申请日：2018-04-03

Applicant: Mohammad A. ABDALLAH

Inventor： Mohammad A. ABDALLAH

IPC: G06F9/30 ,  G06F9/48 ,  G06F9/38 ,  G06F9/34 ,  G06F9/46

CPC classification number: G06F9/30123 ,  G06F9/30043 ,  G06F9/3009 ,  G06F9/30134 ,  G06F9/30138 ,  G06F9/3016 ,  G06F9/34 ,  G06F9/342 ,  G06F9/3808 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/383 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3857 ,  G06F9/3885 ,  G06F9/3891 ,  G06F9/462 ,  G06F9/4843

Abstract: A processor architecture includes a register file hierarchy to implement virtual registers that provide a larger set of registers than those directly supported by an instruction set architecture to facilitate multiple copies of the same architecture register for different processing threads, where the register file hierarchy includes a plurality of hierarchy levels. The processor architecture further includes a plurality of execution units coupled to the register file hierarchy.

公开(公告)号：US10061588B2

公开(公告)日：2018-08-28

申请号：US14100077

申请日：2013-12-09

Applicant: International Business Machines Corporation

Inventor： Michael K Gschwind ,  Valentina Salapura

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/40 ,  G06F9/46

CPC classification number: G06F9/3834 ,  G06F9/30076 ,  G06F9/30105 ,  G06F9/30127 ,  G06F9/30185 ,  G06F9/3832 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/462

Abstract: Operand liveness state information is maintained during context switches for current architected operands of executing programs. The current operand state information indicates whether corresponding current operands are enabled or disabled for use by a first program module comprising machine instructions of an instruction set architecture (ISA) for disabling current architected operands. A machine instruction of the first program module accesses a current operand by using the current operand state information to determine whether a previously stored current operand value is accessible by the first program module.

公开(公告)号：US09886279B2

公开(公告)日：2018-02-06

申请号：US14214045

申请日：2014-03-14

Applicant: Intel Corporation

Inventor： Mohammad Abdallah

IPC: G06F9/46 ,  G06F9/38

CPC classification number: G06F9/3838 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/3867 ,  G06F9/462

Abstract: A method for populating an instruction view data structure by using register template snapshots. The method includes receiving an incoming instruction sequence using a global front end; grouping the instructions to form instruction blocks; using a plurality of register templates to track instruction destinations and instruction sources by populating the register template with block numbers corresponding to the instruction blocks, wherein the block numbers corresponding to the instruction blocks indicate interdependencies among the blocks of instructions; populating and instruction view data structure, wherein the instruction view data structure stores instructions corresponding to the instruction blocks as recorded by the plurality of register templates; and using the instruction view data structure to feed a plurality of stacked execution units of execution stage in accordance with the readiness of instruction sources of the instruction blocks.

公开(公告)号：US09766924B2

公开(公告)日：2017-09-19

申请号：US14792342

申请日：2015-07-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Naotaka Maruyama

IPC: G06F9/46 ,  G06F9/48 ,  G06F9/50

CPC classification number: G06F9/461 ,  G06F9/462 ,  G06F9/4812 ,  G06F9/4843 ,  G06F9/485 ,  G06F9/50

Abstract: A task processor includes a CPU, a save circuit, and a task control circuit. A task control circuit is provided with a task selection circuit and state storage units associated with respective tasks. When executing a predetermined system call instruction, the CPU notifies the task control circuit accordingly. When informed of the execution of a system call instruction, the task control circuit selects a task to be subsequently executed in accordance with an output from the selection circuit. When an interrupt circuit receives a high-speed interrupt request signal, the task switching circuit controls the state transition of a task by executing an interrupt handling instruction designated by the interrupt circuit.

公开(公告)号：US09513911B2

公开(公告)日：2016-12-06

申请号：US14550834

申请日：2014-11-21

Applicant: THALES

Inventor： Philippe Grossi ,  Dominique David ,  Francois Brun

IPC: G06F9/46 ,  G06F9/30 ,  G06F9/48 ,  G06F9/50 ,  G06F21/52

CPC classification number: G06F9/30134 ,  G06F9/3861 ,  G06F9/462 ,  G06F9/4843 ,  G06F9/5016 ,  G06F21/52

Abstract: A method of detecting stack overflows includes the following steps: storing in at least one dedicated register at least one data item chosen from: a data item (SPHaut) indicating a maximum permitted value for a stack pointer, and a data item (SPBas) indicating a minimum permitted value for said stack pointer; effecting a comparison between a current value (SP) or past value (SPMin, SPMax) of said stack pointer and said data item or each of said data items; and generating a stack overflow exception if said comparison indicates that said current or past value of said stack pointer is greater than said maximum permitted value or less than said minimum permitted value. A processor for implementing such a method is also provided.

Abstract translation: 检测堆栈溢出的方法包括以下步骤：在至少一个专用寄存器中存储从以下选择的至少一个数据项：指示堆栈指针的最大允许值的数据项（SPHaut）和指示堆栈指针的数据项（SPBas） 所述堆栈指针的最小允许值; 执行所述堆栈指针的当前值（SP）或过去值（SPMin，SPMax）与所述数据项或所述数据项之间的比较; 以及如果所述比较指示所述堆栈指针的所述当前值或过去值大于所述最大允许值或小于所述最小允许值，则产生堆栈溢出异常。 还提供了一种用于实现这种方法的处理器。

公开(公告)号：US20160224340A1

公开(公告)日：2016-08-04

申请号：US14724061

申请日：2015-05-28

Applicant: Optimum Semiconductor Technologies, Inc.

Inventor： Mayan Moudgill ,  Gary J. Nacer ,  C. John Glossner ,  Arthur Joseph Hoane ,  Sitij Agrawal

IPC: G06F9/30

CPC classification number: G06F15/8053 ,  G06F9/3001 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30101 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30141 ,  G06F9/3836 ,  G06F9/3855 ,  G06F9/461 ,  G06F9/462 ,  G06F15/7828 ,  G06F15/7839 ,  G06F15/8076 ,  G06F17/142

Abstract: A computer processor is disclosed. The computer processor may comprise a vector unit comprising a vector register file comprising at least one register to hold a varying number of elements. The computer processor may further comprise processing logic configured to operate on the varying number of elements in the vector register file using one or more complex arithmetic instructions. The computer processor may be implemented as a monolithic integrated circuit.

Abstract translation: 公开了一种计算机处理器。 计算机处理器可以包括向量单元，其包括向量寄存器文件，其包括至少一个寄存器以保存不同数量的元件。 计算机处理器还可以包括处理逻辑，其被配置为使用一个或多个复数运算指令对矢量寄存器堆中的变化数量的元件进行操作。 计算机处理器可以被实现为单片集成电路。

公开(公告)号：US20160140686A1

公开(公告)日：2016-05-19

申请号：US14543982

申请日：2014-11-18

Applicant: Intel Corporation

Inventor： GUEI-YUAN LUEH ,  SUBRAMANIAM MAIYURAN ,  WEI-YU CHEN ,  KAIYU CHEN

IPC: G06T1/20

CPC classification number: G06F9/462 ,  G06F9/30043 ,  G06F9/30076 ,  G06F9/3009 ,  G06F9/3851

Abstract: Systems and methods may provide for inserting one or more preemption instructions while compiling a computer program. The one or more preemption instructions being inserted within a preemption window in the computer program reduces the number of live registers at each preemption instruction position. Further, the preemption instruction instructs which registers are to be saved at a particular program position, typically the registers that are live at that program position. The compiled program may be run in an execution unit. A preemption request may be made to the execution unit and executed at a next available preemption instruction in the program being run in the execution unit.

Abstract translation: 系统和方法可以提供在编译计算机程序时插入一个或多个抢占指令。 计算机程序中的抢占窗口内插入的一个或多个抢占指令减少了每个抢占指令位置的实时寄存器数量。 此外，抢占指令指示哪些寄存器将被保存在特定的程序位置，通常是存在于该程序位置的寄存器。 编译的程序可以在执行单元中运行。 可以对执行单元进行抢占请求，并且在执行单元中运行的程序中的下一个可用抢占指令下执行抢占请求。

公开(公告)号：US09032417B2

公开(公告)日：2015-05-12

申请号：US13210586

申请日：2011-08-16

Applicant: Takaaki Kawamura

Inventor： Takaaki Kawamura

IPC: G06F9/46 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30123 ,  G06F9/3851 ,  G06F9/462

Abstract: A information processing apparatus having a processor is controlled to execute a procedure of reading from the memory attribute information indicating a usage frequency of a register used by a process to be executed as a next process by the processor when the processor switches a process currently being executed, saving a value of the register used by the next process to be executed by the processor to the memory when the usage frequency of the register indicated by the attribute information is larger than a certain frequency, reading from the memory owner information indicating a process using the register to be used by the next process when the usage frequency of the register indicated by the attribute information is larger than the certain frequency, and restoring a register value saved in the memory to the register when the owner information indicates a process other than the next process.

Abstract translation: 控制具有处理器的信息处理装置，以便当处理器切换当前正在执行的处理时，执行从存储器属性信息读取指示由作为下一个处理执行的处理的处理程序所使用的寄存器的使用频率的过程 当由属性信息指示的寄存器的使用频率大于特定频率时，将由处理器执行的下一处理所使用的寄存器的值保存到存储器，从存储器所有者读取指示使用 当由属性信息指示的寄存器的使用频率大于特定频率时由下一个处理使用的寄存器，以及当所有者信息指示除了该特定频率之外的处理时将保存在存储器中的寄存器值恢复到寄存器 下一个过程。

公开(公告)号：US20150113248A1

公开(公告)日：2015-04-23

申请号：US14584778

申请日：2014-12-29

Applicant: Renesas Electronics Corporation

Inventor： Hideki MATSUYAMA

IPC: G06F13/24 ,  G06F9/38

CPC classification number: G06F13/24 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/327 ,  G06F9/3802 ,  G06F9/461 ,  G06F9/462 ,  G06F9/48

Abstract: A microcomputer includes: a plurality of register lists having a plurality of register patterns, respectively, wherein each of plurality of register patterns designates registers, data of which are to be saved in a data memory; an instruction fetch control circuit configured to fetch instruction code from an instruction memory in response to an interrupt request issued based on occurrence of an interrupt factor; and a register data saving control circuit configured to acquire one register pattern from one of the plurality of register lists in response to the interrupt request, and issue a microinstruction based on the acquired register pattern in response to the interrupt request. An instruction executing section is configured to execute the microinstruction prior to the fetched instruction code, to save the data of registers designated based on the acquired register pattern in the data memory.

Abstract translation: 微型计算机包括：分别具有多个寄存器模式的多个寄存器列表，其中多个寄存器模式中的每一个指定寄存器，其数据将被保存在数据存储器中; 指令获取控制电路，被配置为响应于基于中断因素的发生而发出的中断请求，从指令存储器取出指令代码; 以及寄存器数据保存控制电路，配置为响应于所述中断请求从所述多个寄存器列表中的一个寄存器列表获取一个寄存器模式，并且响应于所述中断请求，基于所获取的寄存器模式发出微指令。 指令执行部分被配置为在获取的指令代码之前执行微指令，以将基于所获取的寄存器模式指定的寄存器的数据保存在数据存储器中。