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公开(公告)号：US09043543B2
公开(公告)日：2015-05-26
申请号：US13113546
申请日：2011-05-23
CPC分类号： G06F3/061 , G06F3/0638 , G06F3/0661 , G06F3/0689 , G06F11/1076 , G06F11/2089 , G06F2211/1057 , G06F2211/1059 , G11B2020/1222 , G11B2220/415
摘要： A Redundant Array of Independent Disks (RAID) controller receives new data that is to be written, wherein the new data is indicated in blocks of a first block size. The RAID controller reads old data, and old parity that corresponds to the old data, stored in blocks of a second block size that is larger in size than the first block size. The RAID controller computes new parity based on the new data, the old data, and the old parity. The RAID controller writes the new data and the new parity aligned to the blocks of the second block size, wherein portions of the old data that are not overwritten by the RAID controller are also written to the blocks of the second block size.
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2.发明授权公开(公告)号：US08856479B2
公开(公告)日：2014-10-07
申请号：US13451738
申请日：2012-04-20
CPC分类号： G06F13/28 , G06F3/061 , G06F3/0656 , G06F3/0658 , G06F3/0659 , G06F3/0689 , G06F9/3857 , G06F13/126
摘要： A method and controller for implementing storage adapter performance optimization with chained hardware operations completion coalescence, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines, and a processor. A plurality of the command blocks are selectively arranged by firmware in a predefined chain including a plurality of simultaneous command blocks. All of the simultaneous command blocks are completed in any order by respective hardware engines, then the next command block in the predefined chain is started under hardware control without any hardware-firmware (HW-FW) interlocking with the simultaneous command block completion coalescence.
摘要翻译： 一种用于实现具有链接的硬件操作完成聚结的存储适配器性能优化的方法和控制器，以及提供主题控制器电路所在的设计结构。 控制器包括多个硬件引擎和处理器。 多个命令块通过包括多个同时命令块的预定链中的固件选择性地排列。 所有的同时命令块按照各个硬件引擎的任何顺序完成，则预定义链中的下一个命令块在硬件控制下启动，而不需要与同时命令块完成合并联锁的任何硬件固件（HW-FW）。
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3.发明授权Implementing storage adapter performance optimization with enhanced resource pool allocation 有权通过增强资源池分配来实现存储适配器性能优化公开(公告)号：US08793462B2
公开(公告)日：2014-07-29
申请号：US13114427
申请日：2011-05-24
申请人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith, II , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
发明人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith, II , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
CPC分类号： G06F3/0617 , G06F3/0631 , G06F3/0689
摘要： A method and controller for implementing storage adapter performance optimization with enhanced resource pool allocation, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; a processor, and a plurality of resource pools. A plurality of work queues is associated with the resource pools. The processor initializes a list of types, and the associated amount of pages for each allocate type. The hardware engines maintain a count of allocate types, specifying a type on each allocation and deallocation, and performing allocation from the resource pools for deadlock avoidance.
摘要翻译： 一种用于实现具有增强的资源池分配的存储适配器性能优化的方法和控制器，以及提供主题控制器电路所在的设计结构。 控制器包括多个硬件引擎; 处理器和多个资源池。 多个工作队列与资源池相关联。 处理器初始化类型列表，以及每种分配类型的相关联的页面数量。 硬件引擎维护分配类型的计数，指定每个分配和解除分配的类型，并从资源池执行死锁避免的分配。
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4.发明授权Method for communicating with a network adapter using a queue data structure and cached address translations 有权使用队列数据结构和缓存地址转换与网络适配器进行通信的方法公开(公告)号：US08769168B2
公开(公告)日：2014-07-01
申请号：US11550191
申请日：2006-10-17
IPC分类号： G06F12/00
CPC分类号： G06F13/102
摘要： Mechanisms for communicating with a network adapter using a queue data structure are provided. A device driver invokes device driver services for initializing address translation and protection table (ATPT) entries in a root complex for the queue data structure. The device driver services return untranslated addresses to the device driver which are in turn provided to the network adapter. In response to retrieving a queue element from the queue data structure, the network adapter may request a translation of an untranslated address specified in the queue element and store the translated address in the network adapter prior to receiving a data packet targeting a buffer associated with the queue element.
摘要翻译： 提供了使用队列数据结构与网络适配器进行通信的机制。 设备驱动程序调用设备驱动程序服务以初始化队列数据结构的根组合中的地址转换和保护表（ATPT）条目。 设备驱动程序服务将未翻译的地址返回给设备驱动程序，这些设备驱动程序又提供给网络适配器。 响应于从队列数据结构检索队列元素，网络适配器可以请求在队列元素中指定的非翻译地址的转换，并且在接收到针对与 队列元素
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5.发明申请IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH HARDWARE OPERATIONS COMPLETION COALESCENCE 有权实施存储适配器性能优化与硬件操作完成COALESCENCE公开(公告)号：US20130282969A1
公开(公告)日：2013-10-24
申请号：US13451738
申请日：2012-04-20
CPC分类号： G06F13/28 , G06F3/061 , G06F3/0656 , G06F3/0658 , G06F3/0659 , G06F3/0689 , G06F9/3857 , G06F13/126
摘要： A method and controller for implementing storage adapter performance optimization with chained hardware operations completion coalescence, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines, and a processor. A plurality of the command blocks are selectively arranged by firmware in a predefined chain including a plurality of simultaneous command blocks. All of the simultaneous command blocks are completed in any order by respective hardware engines, then the next command block in the predefined chain is started under hardware control without any hardware-firmware (HW-FW) interlocking with the simultaneous command block completion coalescence.
摘要翻译： 一种用于实现具有链接的硬件操作完成聚结的存储适配器性能优化的方法和控制器，以及提供主题控制器电路所在的设计结构。 控制器包括多个硬件引擎和处理器。 多个命令块通过包括多个同时命令块的预定链中的固件选择性地排列。 所有的同时命令块按照各个硬件引擎的任何顺序完成，则预定义链中的下一个命令块在硬件控制下启动，而不需要与同时命令块完成合并联锁的任何硬件固件（HW-FW）。
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6.发明申请WRITING NEW DATA OF A FIRST BLOCK SIZE TO A SECOND BLOCK SIZE USING A WRITE-WRITE MODE 有权使用写入模式将第一块大小的新数据写入第二块大小公开(公告)号：US20130219119A1
公开(公告)日：2013-08-22
申请号：US13402465
申请日：2012-02-22
CPC分类号： G06F3/061 , G06F3/0656 , G06F3/0689 , G06F11/1076 , G06F2211/1057
摘要： Apparatuses and methods to write new data of a first block size are provided. A particular method may include writing old data from a destination block of a second block size of a data drive to a first buffer of the second block size. The old data may be written according to address information of the old data and without overwriting the new data in the first buffer. The method may further include writing zeros to a second buffer of the second block size according to the address information of the old data. The zeros written in the second buffer may correspond with the old data written in the first buffer.
摘要翻译： 提供了写入第一块大小的新数据的装置和方法。 特定方法可以包括将来自数据驱动器的第二块大小的目的地块的旧数据写入到第二块大小的第一缓冲器。 旧数据可以根据旧数据的地址信息进行写入，而不会覆盖第一缓冲器中的新数据。 该方法还可以包括根据旧数据的地址信息将零写入第二块大小的第二缓冲器。 写在第二缓冲器中的零可对应于写在第一缓冲器中的旧数据。
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公开(公告)号：US08489946B2
公开(公告)日：2013-07-16
申请号：US13614805
申请日：2012-09-13
IPC分类号： G11C29/00
CPC分类号： G06F11/1092 , G06F2211/1057 , G06F2211/1059
摘要： At least one standard size data block of a storage device is scanned for a logically bad pattern. If the logically pad pattern is detected, a block address that is associated with the standard size data block is added to a bad block table. If the logically pad pattern is not detected, it may be determined if the block address associated with the standard size data block is in the bad block table. If the logically pad pattern is not detected and if the block address associated with the standard size data block is in the bad block table, the block address may be removed from the bad block table. The logically bad pattern may have a first predefined data portion and a second predefined data portion and may be repeated the requisite number of instances to fill the standard size data block.
摘要翻译： 扫描存储设备的至少一个标准尺寸数据块以获得逻辑不良图案。 如果检测到逻辑焊盘图案，则将与标准尺寸数据块相关联的块地址添加到坏块表。 如果没有检测到逻辑填充图案，则可以确定与标准尺寸数据块相关联的块地址是否在坏块表中。 如果没有检测到逻辑上的焊盘图案，并且如果与标准尺寸数据块相关联的块地址在坏块表中，则块地址可以从坏块表中去除。 逻辑不良图案可以具有第一预定义数据部分和第二预定义数据部分，并且可以重复必需数量的实例以填充标准尺寸数据块。
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公开(公告)号：US20130007545A1
公开(公告)日：2013-01-03
申请号：US13614805
申请日：2012-09-13
CPC分类号： G06F11/1092 , G06F2211/1057 , G06F2211/1059
摘要： At least one standard size data block of a storage device is scanned for a logically bad pattern. If the logically pad pattern is detected, a block address that is associated with the standard size data block is added to a bad block table. If the logically pad pattern is not detected, it may be determined if the block address associated with the standard size data block is in the bad block table. If the logically pad pattern is not detected and if the block address associated with the standard size data block is in the bad block table, the block address may be removed from the bad block table. The logically bad pattern may have a first predefined data portion and a second predefined data portion and may be repeated the requisite number of instances to fill the standard size data block.
摘要翻译： 扫描存储设备的至少一个标准尺寸数据块以获得逻辑不良图案。 如果检测到逻辑焊盘图案，则将与标准尺寸数据块相关联的块地址添加到坏块表。 如果没有检测到逻辑填充图案，则可以确定与标准尺寸数据块相关联的块地址是否在坏块表中。 如果没有检测到逻辑上的焊盘图案，并且如果与标准尺寸数据块相关联的块地址在坏块表中，则块地址可以从坏块表中去除。 逻辑不良图案可以具有第一预定义数据部分和第二预定义数据部分，并且可以重复必需数量的实例以填充标准尺寸数据块。
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公开(公告)号：US20120303890A1
公开(公告)日：2012-11-29
申请号：US13113546
申请日：2011-05-23
IPC分类号： G06F12/16
CPC分类号： G06F3/061 , G06F3/0638 , G06F3/0661 , G06F3/0689 , G06F11/1076 , G06F11/2089 , G06F2211/1057 , G06F2211/1059 , G11B2020/1222 , G11B2220/415
摘要： A Redundant Array of Independent Disks (RAID) controller receives new data that is to be written, wherein the new data is indicated in blocks of a first block size. The RAID controller reads old data, and old parity that corresponds to the old data, stored in blocks of a second block size that is larger in size than the first block size. The RAID controller computes new parity based on the new data, the old data, and the old parity. The RAID controller writes the new data and the new parity aligned to the blocks of the second block size, wherein portions of the old data that are not overwritten by the RAID controller are also written to the blocks of the second block size.
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10.发明申请IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH PARITY UPDATE FOOTPRINT MIRRORING 有权实现存储适配器性能优化与更新FOOTPRINT MIRRORING公开(公告)号：US20120303859A1
公开(公告)日：2012-11-29
申请号：US13114268
申请日：2011-05-24
申请人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
发明人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
IPC分类号： G06F12/00
CPC分类号： G06F11/1076 , G06F11/1666 , G06F11/2089 , G06F11/2097 , G06F2211/1009 , G06F2211/1057 , G06F2211/1059
摘要： A method and controller for implementing storage adapter performance optimization with parity update footprint mirroring between dual adapters minimizing firmware operations, and a design structure on which the subject controller circuit resides are provided. Each of a first controller and a second controller includes a plurality of hardware engines, a control store configured to store parity update footprint (PUFP) data; a data store; and a nonvolatile random access memory (NVRAM). One controller operates in a first initiator mode for transferring PUFP data to the other controller operating in a target mode. Respective initiator hardware engines transfers PUFP data from the initiator control store, selectively updating PUFP data, and writing PUFP data to the initiator data store and to the initiator NVRAM, and simultaneously transmitting PUFP data to the other controller. Respective target hardware engines write PUFP data to the target data store and the target NVRAM, eliminating firmware operations.
摘要翻译： 一种用于实现存储适配器性能优化的方法和控制器，其中，具有奇偶校验更新占用面积的双重适配器之间的镜像，最小化固件操作，以及提供了主题控制器电路所在的设计结构。 第一控制器和第二控制器中的每一个包括多个硬件引擎，配置为存储奇偶校验更新占位（PUFP）数据的控制存储器; 数据存储 和非易失性随机存取存储器（NVRAM）。 一个控制器以第一启动器模式操作，用于将PUFP数据传送到以目标模式操作的另一个控制器。 各启动器硬件引擎从启动器控制存储器传输PUFP数据，选择性地更新PUFP数据，并将PUFP数据写入发起者数据存储器和发起者NVRAM，同时将PUFP数据传输到另一个控制器。 各个目标硬件引擎将PUFP数据写入目标数据存储和目标NVRAM，从而消除了固件操作。
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