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公开(公告)号：US06496955B1
公开(公告)日：2002-12-17
申请号：US09595150
申请日：2000-06-16
IPC分类号： G06F1750
CPC分类号： G06F17/504
摘要： A method for constructing a latch mapping between a first level description and a second level description of a digital system, wherein the first level description and the second level descriptions identify components in the digital system using a predefined naming convention, is provided. The method includes identifying first latch components in the first level description and, for each identified first latch component, storing a first string comprising a selected property of the first latch component in a first storage. The method further includes identifying second latch components in the second level description and, for each second latch component, storing a second string comprising a selected property of the second latch component in a second storage. The method further includes generating a latch mapping by matching the first strings in the first storage with the second strings in the second storage.
摘要翻译： 提供了一种在数字系统的第一级描述和第二级描述之间构建锁存映射的方法，其中第一级描述和第二级描述使用预定义的命名约定识别数字系统中的组件。 该方法包括识别第一级描述中的第一锁存器组件，并且对于每个识别的第一锁存器组件，将包括第一锁存器组件的选定属性的第一串存储在第一存储器中。 该方法还包括识别第二级描述中的第二锁存器组件，并且对于每个第二锁存器组件，在第二存储器中存储包括第二锁存器组件的选定属性的第二串。 该方法还包括通过将第一存储器中的第一字符串与第二存储器中的第二字符串进行匹配来生成锁存器映射。
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2.发明授权Mechanism for delivering precise exceptions in an out-of-order processor with speculative execution 有权在具有推测性执行的无序处理器中提供精确异常的机制公开(公告)号：US06615343B1
公开(公告)日：2003-09-02
申请号：US09599227
申请日：2000-06-22
IPC分类号： G06F938
CPC分类号： G06F9/3861 , G06F9/3842
摘要： A method of handling an exception in a processor includes setting a state upon detection of an exception, signaling a trap for the exception if the state is set, and based on a class of the exception, processing the exception differently before signaling the trap. The method may include replaying an instruction causing the exception before signaling the trap for the exception based on the class of the exception. The method may include replaying the instruction causing the exception after the instruction causing the exception becomes an oldest, unretired instruction. The method may include signaling the trap for the exception after an instruction causing the exception becomes an oldest, unretired instruction. The method may include marking an instruction causing the exception as complete without issuing the instruction causing the exception. An apparatus for handling exceptions in a processor includes an instruction scheduler for setting a state upon detection of an exception and signaling a trap for the exception if the state is set. The instruction scheduler, based on a class of the exception, processes the exception differently before signaling the trap.
摘要翻译： 在处理器中处理异常的方法包括在检测到异常时设置状态，如果状态被设置则发信号通知异常的陷阱，并且基于异常类，在发信号通知之前不同地处理异常。 该方法可以包括在基于异常的类发送异常的陷阱之前重放导致异常的指令。 该方法可以包括在导致异常的指令成为最旧的未命令指令之后重放导致异常的指令。 该方法可以包括在导致异常的指令成为最旧的未命令指令之后发信号通知异常的陷阱。 该方法可以包括将导致异常的指令标记为完整，而不发出导致异常的指令。 用于在处理器中处理异常的装置包括指令调度器，用于在检测到异常时设置状态，并且如果状态被设置，则发送异常的陷阱。 指令调度程序基于异常类，在通知陷阱之前处理异常。
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3.发明授权Storing results of producer instructions to facilitate consumer instruction dependency tracking 有权存储生产者指令的结果以便于消费者指令依赖跟踪公开(公告)号：US07237096B1
公开(公告)日：2007-06-26
申请号：US10818043
申请日：2004-04-05
IPC分类号： G06F9/30
CPC分类号： G06F9/30181 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： If a consumer instruction specifies a 64 bit source register comprised of results provided by two 32 bit producer instructions, the number of dependencies that must be tracked per source register can be decreased by transforming one or more of the 32 bit producer instructions so that rather than simply storing its result in a 32 bit destination register, the transformed instruction stores its result into a 64 bit logical register along with another 32 bit value held in another 32 bit register.
摘要翻译： 如果消费者指令指定由两个32位生产者指令提供的结果组成的64位源寄存器，则可以通过转换一个或多个32位生产者指令来减少每个源寄存器必须跟踪的依赖关系的数量， 简单地将其结果存储在32位目标寄存器中，变换后的指令将其结果存储到64位逻辑寄存器以及另一个32位寄存器中保存的另一个32位值。
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