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公开(公告)号：US20110264720A1
公开(公告)日：2011-10-27
申请号：US11323994
申请日：2005-12-30
申请人： Wajdi Feghali , William C. Hasenplaugh , Gilbert M. Wolrich , Daniel R. Cutter , Vinodh Gopal , Gunnar Gaubatz
发明人： Wajdi Feghali , William C. Hasenplaugh , Gilbert M. Wolrich , Daniel R. Cutter , Vinodh Gopal , Gunnar Gaubatz
CPC分类号： G06F7/5275
摘要： In general, in one aspect, the disclosure describes a multiplier that includes a set of multiple multipliers configured in parallel where the set of multiple multipliers have access to a first operand and a second operand to multiply, the first operand having multiple segments and the second operand having multiple segments. The multiplier also includes logic to repeatedly supply a single segment of the second operand to each multiplier of the set of multiple multipliers and to supply multiple respective segments of the first operand to the respective ones of the set of multiple multipliers until each segment of the second operand has been supplied with each segment of the first operand. The logic shifts the output of different ones of the set of multiple multipliers based, at least in part, on the position of the respective segments within the first operand. The multiplier also includes an accumulator coupled to the logic.
摘要翻译： 通常，在一个方面，本发明描述了一种乘法器，其包括并行配置的一组多个乘法器，其中多个乘法器的组具有访问第一操作数和第二操作数以乘以具有多个段的第一操作数和第二操作数 具有多个段的操作数。 所述乘法器还包括逻辑以将所述第二操作数的单个段重复地提供给所述多个乘法器集合的每个乘法器，并且将所述第一操作数的多个相应段提供给所述多个乘法器组中的相应一个，直到所述第二 操作数已被提供给第一个操作数的每个段。 该逻辑至少部分地基于第一操作数内的相应段的位置来移动多个乘法器中的不同乘法器的输出。 乘法器还包括耦合到逻辑的累加器。
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公开(公告)号：US07725624B2
公开(公告)日：2010-05-25
申请号：US11323993
申请日：2005-12-30
申请人： Wajdi K. Feghali , William C. Hasenplaugh , Gilbert M. Wolrich , Daniel R. Cutter , Vinodh Gopal , Gunnar Gaubatz
发明人： Wajdi K. Feghali , William C. Hasenplaugh , Gilbert M. Wolrich , Daniel R. Cutter , Vinodh Gopal , Gunnar Gaubatz
CPC分类号： G06F7/52 , G06F9/3001 , G06F9/3881 , G06F9/3885 , G06F21/72
摘要： In general, in one aspect, the disclosure describes a system including multiple programmable processing units, a dedicated hardware multiplier, and at least one bus connecting the multiple processing units and multiplier.
摘要翻译： 通常，在一个方面，本公开描述了包括多个可编程处理单元，专用硬件乘法器和连接多个处理单元和乘法器的至少一个总线的系统。
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公开(公告)号：US08073892B2
公开(公告)日：2011-12-06
申请号：US11323994
申请日：2005-12-30
申请人： Wajdi K. Feghali , William C. Hasenplaugh , Gilbert M. Wolrich , Daniel R. Cutter , Vinodh Gopal , Gunnar Gaubatz
发明人： Wajdi K. Feghali , William C. Hasenplaugh , Gilbert M. Wolrich , Daniel R. Cutter , Vinodh Gopal , Gunnar Gaubatz
IPC分类号： G06F7/52
CPC分类号： G06F7/5275
摘要： In general, in one aspect, the disclosure describes a multiplier that includes a set of multiple multipliers configured in parallel where the set of multiple multipliers have access to a first operand and a second operand to multiply, the first operand having multiple segments and the second operand having multiple segments. The multiplier also includes logic to repeatedly supply a single segment of the second operand to each multiplier of the set of multiple multipliers and to supply multiple respective segments of the first operand to the respective ones of the set of multiple multipliers until each segment of the second operand has been supplied with each segment of the first operand. The logic shifts the output of different ones of the set of multiple multipliers based, at least in part, on the position of the respective segments within the first operand. The multiplier also includes an accumulator coupled to the logic.
摘要翻译： 通常，在一个方面，本发明描述了一种乘法器，其包括并行配置的一组多个乘法器，其中多个乘法器的组具有访问第一操作数和第二操作数以乘以具有多个段的第一操作数和第二操作数 具有多个段的操作数。 所述乘法器还包括逻辑以将所述第二操作数的单个段重复地提供给所述多个乘法器集合的每个乘法器，并且将所述第一操作数的多个相应段提供给所述多个乘法器组中的相应一个，直到所述第二 操作数已被提供给第一个操作数的每个段。 该逻辑至少部分地基于第一操作数内的相应段的位置来移动多个乘法器中的不同乘法器的输出。 乘法器还包括耦合到逻辑的累加器。
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