利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

41 条记录 (耗时 0.029 秒)

    Cryptographic system, method and multiplier
    1.
    发明授权
    Cryptographic system, method and multiplier 有权
    加密系统，方法和乘数

    公开(公告)号：US08073892B2

    公开(公告)日：2011-12-06

    申请号：US11323994

    申请日：2005-12-30

    申请人： Wajdi K. Feghali ,  William C. Hasenplaugh ,  Gilbert M. Wolrich ,  Daniel R. Cutter ,  Vinodh Gopal ,  Gunnar Gaubatz

    发明人： Wajdi K. Feghali ,  William C. Hasenplaugh ,  Gilbert M. Wolrich ,  Daniel R. Cutter ,  Vinodh Gopal ,  Gunnar Gaubatz

    IPC分类号： G06F7/52

    CPC分类号： G06F7/5275

    摘要： In general, in one aspect, the disclosure describes a multiplier that includes a set of multiple multipliers configured in parallel where the set of multiple multipliers have access to a first operand and a second operand to multiply, the first operand having multiple segments and the second operand having multiple segments. The multiplier also includes logic to repeatedly supply a single segment of the second operand to each multiplier of the set of multiple multipliers and to supply multiple respective segments of the first operand to the respective ones of the set of multiple multipliers until each segment of the second operand has been supplied with each segment of the first operand. The logic shifts the output of different ones of the set of multiple multipliers based, at least in part, on the position of the respective segments within the first operand. The multiplier also includes an accumulator coupled to the logic.

    摘要翻译： 通常，在一个方面，本发明描述了一种乘法器，其包括并行配置的一组多个乘法器，其中多个乘法器的组具有访问第一操作数和第二操作数以乘以具有多个段的第一操作数和第二操作数 具有多个段的操作数。 所述乘法器还包括逻辑以将所述第二操作数的单个段重复地提供给所述多个乘法器集合的每个乘法器，并且将所述第一操作数的多个相应段提供给所述多个乘法器组中的相应一个，直到所述第二 操作数已被提供给第一个操作数的每个段。 该逻辑至少部分地基于第一操作数内的相应段的位置来移动多个乘法器中的不同乘法器的输出。 乘法器还包括耦合到逻辑的累加器。

    Executing instruction for processing by ALU accessing different scope of variables using scope index automatically changed upon procedure call and exit
    3.
    发明授权
    Executing instruction for processing by ALU accessing different scope of variables using scope index automatically changed upon procedure call and exit 失效
    通过ALU访问使用范围索引访问不同范围的变量的执行指令在过程调用和退出时自动更改

    公开(公告)号：US07475229B2

    公开(公告)日：2009-01-06

    申请号：US11354670

    申请日：2006-02-14

    申请人： Wajdi K. Feghali ,  William C. Hasenplaugh ,  Gilbert M. Wolrich ,  Daniel F. Cutter ,  Vinodh Gopal ,  Gunnar Gaubatz

    发明人： Wajdi K. Feghali ,  William C. Hasenplaugh ,  Gilbert M. Wolrich ,  Daniel F. Cutter ,  Vinodh Gopal ,  Gunnar Gaubatz

    IPC分类号： G06F9/302

    CPC分类号： G06F21/602

    摘要： In general, in one aspect, the disclosure describes a processing unit that includes a memory, an arithmetic logic unit, and control logic having access to program instructions of a control store. The control logic includes logic to access multiple sets of variables, variables in the different sets of variables being identically referenced by instructions, associate a one of the sets of variables as the current set of variables to be used in instructions that are executed by the arithmetic logic unit, change the set of variables associated with the current set of variables in response to a procedure call or exit, and alter the value of a variable of a set of the variables other than the set of variables associated with the current set of variables in response to an instruction.

    摘要翻译： 通常，在一个方面，本公开描述了一种处理单元，其包括存储器，算术逻辑单元和具有访问控制存储器的程序指令的控制逻辑。 控制逻辑包括访问多组变量的逻辑，不同变量集合中的变量由指令相同地引用，将变量集合中的一个与当前由算术执行的指令中使用的变量集合相关联 逻辑单元，响应于过程调用或退出而改变与当前变量集相关联的变量集合，并且改变一组变量的值，而不是与当前变量集合相关联的变量集合 响应一个指令。

    CRYPTOGRAPHIC SYSTEM, METHOD AND MULTIPLIER
    4.
    发明申请
    CRYPTOGRAPHIC SYSTEM, METHOD AND MULTIPLIER 有权
    CRYPTOGRAPHIC系统，方法和乘法器

    公开(公告)号：US20110264720A1

    公开(公告)日：2011-10-27

    申请号：US11323994

    申请日：2005-12-30

    申请人： Wajdi Feghali ,  William C. Hasenplaugh ,  Gilbert M. Wolrich ,  Daniel R. Cutter ,  Vinodh Gopal ,  Gunnar Gaubatz

    发明人： Wajdi Feghali ,  William C. Hasenplaugh ,  Gilbert M. Wolrich ,  Daniel R. Cutter ,  Vinodh Gopal ,  Gunnar Gaubatz

    IPC分类号： G06F7/52 ,  G06F5/01

    CPC分类号： G06F7/5275

    摘要： In general, in one aspect, the disclosure describes a multiplier that includes a set of multiple multipliers configured in parallel where the set of multiple multipliers have access to a first operand and a second operand to multiply, the first operand having multiple segments and the second operand having multiple segments. The multiplier also includes logic to repeatedly supply a single segment of the second operand to each multiplier of the set of multiple multipliers and to supply multiple respective segments of the first operand to the respective ones of the set of multiple multipliers until each segment of the second operand has been supplied with each segment of the first operand. The logic shifts the output of different ones of the set of multiple multipliers based, at least in part, on the position of the respective segments within the first operand. The multiplier also includes an accumulator coupled to the logic.

    摘要翻译： 通常，在一个方面，本发明描述了一种乘法器，其包括并行配置的一组多个乘法器，其中多个乘法器的组具有访问第一操作数和第二操作数以乘以具有多个段的第一操作数和第二操作数 具有多个段的操作数。 所述乘法器还包括逻辑以将所述第二操作数的单个段重复地提供给所述多个乘法器集合的每个乘法器，并且将所述第一操作数的多个相应段提供给所述多个乘法器组中的相应一个，直到所述第二 操作数已被提供给第一个操作数的每个段。 该逻辑至少部分地基于第一操作数内的相应段的位置来移动多个乘法器中的不同乘法器的输出。 乘法器还包括耦合到逻辑的累加器。

    Modular reduction using folding
    6.
    发明申请
    Modular reduction using folding 有权
    使用折叠模块化减少

    公开(公告)号：US20070297601A1

    公开(公告)日：2007-12-27

    申请号：US11476432

    申请日：2006-06-27

    申请人： William C. Hasenplaugh ,  Gunnar Gaubatz ,  Vinodh Gopal

    发明人： William C. Hasenplaugh ,  Gunnar Gaubatz ,  Vinodh Gopal

    IPC分类号： H04L9/28

    CPC分类号： G06F7/72

    摘要： Techniques are described to determine N mod M, where N is a number having a width of n-bits, and M is a number having a width of m-bits. The techniques, generally, involve determining N′=NH2f mod M+NL and, subsequently, determining N′ mod M

    摘要翻译： 描述技术来确定N mod M，其中N是具有n位宽度的数，M是具有m位宽度的数。 这些技术通常涉及确定N'= N H 2 H 2 mod M + N L L，并且随后确定N'mod M

    Modular reduction using folding
    8.
    发明授权
    Modular reduction using folding 有权
    使用折叠模块化减少

    公开(公告)号：US08229109B2

    公开(公告)日：2012-07-24

    申请号：US11476432

    申请日：2006-06-27

    申请人： William C. Hasenplaugh ,  Gunnar Gaubatz ,  Vinodh Gopal

    发明人： William C. Hasenplaugh ,  Gunnar Gaubatz ,  Vinodh Gopal

    IPC分类号： G06F7/72

    CPC分类号： G06F7/72

    摘要： Techniques are described to determine N mod M, where N is a number having a width of n-bits, and M is a number having a width of m-bits. The techniques, generally, involve determining N′=Nrt2f mod M+NL and, subsequently, determining N′ mod M.

    摘要翻译： 描述技术来确定N mod M，其中N是具有n位宽度的数，M是具有m位宽度的数。 这些技术通常涉及确定N'= Nrt2f mod M + NL，并且随后确定N'mod M.