公开(公告)号：US06662319B1

公开(公告)日：2003-12-09

申请号：US09652314

申请日：2000-08-31

Applicant: David Arthur James Webb, Jr. ,  Richard E. Kessler ,  Steve Lang

Inventor： David Arthur James Webb, Jr. ,  Richard E. Kessler ,  Steve Lang

IPC: G06F1110

CPC classification number: G06F11/0763 ,  G06F11/0724

Abstract: A multi-processor system in which each processor receives a message from another processor in the system. The message may contain corrupted data that was corrupted during transmission from the preceding processor. Upon receiving the message, the processor detects that a portion of the message contains corrupted data. The processor then replaces the corrupted portion with a predetermined bit pattern known or otherwise programmed into all other processors in the system. The predetermined bit pattern indicates that the associated portion of data was corrupted. The processor that detects the error in the message preferably alerts the system that an error has been detected. The message now containing the predetermined bit pattern in place of the corrupted data is retransmitted to another processor. The predetermined bit pattern will indicate that an error in the message was detected by the previous processor. In response, the processor detecting the predetermined bit pattern preferably will not alert the system of the existence of an error. The same message with the predetermined bit pattern can be retransmitted to other processors which also will detect the presence of the predetermined bit pattern and in response not alert the system of the presence of an error. As such, because only the first processor to detect an error alerts the system of the error and because messages containing uncorrectable errors still are transmitted through the system, fault isolation is improved and the system is less likely to fall into a deadlock condition.

Abstract translation: 一种多处理器系统，其中每个处理器从系统中的另一处理器接收消息。 消息可能包含在从前一个处理器传输过程中损坏的损坏的数据。 处理器收到消息后，检测到消息的一部分包含损坏的数据。 然后，处理器以已知或以其他方式编程到系统中的所有其他处理器的预定位模式来替换被破坏的部分。 预定位模式指示相关联的数据部分已损坏。 检测消息中的错误的处理器最好提醒系统检测到错误。 现在包含预定位模式以代替已损坏数据的消息被重新发送到另一个处理器。 预定的位模式将指示消息中的错误被先前的处理器检测到。 作为响应，优选地，检测预定位模式的处理器不会警告系统存在错误。 具有预定位模式的相同消息可以被重新发送到其他处理器，其也将检测预定位模式的存在，并且在响应时不向系统警告存在错误。 因此，由于只有第一个处理器检测错误才会使系统发生错误，并且由于包含不可校正错误的消息仍然通过系统传输，所以故障隔离得到改善，系统不太可能陷入死锁状态。

公开(公告)号：US5924120A

公开(公告)日：1999-07-13

申请号：US18320

申请日：1998-02-03

Applicant: Rahul Razdan ,  David Arthur James Webb, Jr. ,  James Keller ,  Derrick R. Meyer

Inventor： Rahul Razdan ,  David Arthur James Webb, Jr. ,  James Keller ,  Derrick R. Meyer

IPC: G06F9/38 ,  G06F12/08 ,  G06F9/40 ,  G06F12/04

CPC classification number: G06F12/0897 ,  G06F9/3869

Abstract: Use of an internal processor data bus is maximized in a system where external transactions may occur at a rate which is fractionally slower than the rate of the internal transactions. The technique inserts a selectable delay element in the signal path during an external operation such as a cache fill operation. The one cycle delay provides a time slot in which an internal operation, such as a load from an internal cache, may be performed. This technique therefore permits full use of the time slots on the internal data bus. It can, for, example, allow load operations to begin at a much earlier time than would otherwise be possible in architectures where fill operations can consume multiple bus time slots.

Abstract translation: 在内部处理器数据总线的使用最大化的系统中，外部事务可能以比内部事务的速度慢的速度发生。 该技术在诸如高速缓存填充操作的外部操作期间在信号路径中插入可选择的延迟元件。 一个周期延迟提供了可以执行内部操作（例如来自内部高速缓存的负载）的时隙。 因此，该技术允许充分利用内部数据总线上的时隙。 例如，它可以允许加载操作在比填充操作可以消耗多个总线时隙的体系结构中更早的时间开始。

公开(公告)号：US06401173B1

公开(公告)日：2002-06-04

申请号：US09237519

申请日：1999-01-26

Applicant: Rahul Razdan ,  David Arthur James Webb, Jr. ,  James B. Keller

Inventor： Rahul Razdan ,  David Arthur James Webb, Jr. ,  James B. Keller

IPC: G06F1200

CPC classification number: G06F12/0897

Abstract: An architecture which splits primary and secondary cache memory buses and maintains cache hierarchy consistency without performing an explicit invalidation of the secondary cache tag. Two explicit rules are used to determine the status of a block read from the primary cache. In particular, if any memory reference subset matches a block in the primary cache, the associated secondary cache block is ignored. Secondly, if any memory reference subset matches a block in the miss address file, the associated secondary cache block is ignored. Therefore, any further references which subset match the first reference are not allowed to proceed until the fill back to main memory has been completed and the associated miss address file entry has been retired. This ensures that no agent in the host processor or an external agent can illegally use the stale secondary cache data.

Abstract translation: 分割主缓冲存储器总线和次高速缓存存储器总线并维持高速缓存层次一致性而不执行次级高速缓存标签的明确无效的架构。 使用两个显式规则来确定从主缓存读取的块的状态。 特别地，如果任何存储器引用子集与主缓存中的块匹配，则相关联的二级高速缓存块将被忽略。 其次，如果任何存储器引用子集匹配未命中地址文件中的块，则关联的二级高速缓存块将被忽略。 因此，任何进一步的引用哪个子集匹配第一个引用不允许继续，直到填充回主存储器已经完成并且相关的未命中地址文件条目已经退休。 这确保主机处理器或外部代理中的代理不会非法使用过时的二级高速缓存数据。

公开(公告)号：US6141734A

公开(公告)日：2000-10-31

申请号：US17752

申请日：1998-02-03

Applicant: Rahul Razdan ,  David Arthur James Webb, Jr. ,  James Keller ,  Derrick R. Meyer ,  Daniel Lawrence Leibholz

Inventor： Rahul Razdan ,  David Arthur James Webb, Jr. ,  James Keller ,  Derrick R. Meyer ,  Daniel Lawrence Leibholz

IPC: G06F12/08 ,  G06F13/00

CPC classification number: G06F12/0815 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087

Abstract: A technique for implementing load-locked and store-conditional instruction primitives by using a local cache for information about exclusive ownership. The valid bit in particular provides information to properly execute load-locked and store-conditional instructions without the need for lock flag or local lock address registers for each individual locked address. Integrity of locked data is accomplished by insuring that load-locked and store-conditional instructions are processed in order, that no internal agents can evict blocks from a local cache as a side effect as their processing, that external agents update the context of cache memories first using invalidating probe commands, and that only non-speculative instructions are permitted to generate external commands.

Abstract translation: 一种用于通过使用本地缓存来获取关于独占所有权的信息来实现加载锁定和存储条件指令原语的技术。 有效位特别提供了正确执行加载锁定和存储条件指令的信息，而不需要锁定标志或每个单独锁定地址的本地锁定地址寄存器。 锁定数据的完整性通过确保按顺序处理加载锁定和存储条件指令来实现，即内部代理可以将本地缓存中的块作为其处理的副作用来驱逐块，外部代理更新缓存存储器的上下文 首先使用无效探测命令，并且只允许非推测性指令生成外部命令。

公开(公告)号：US07093105B2

公开(公告)日：2006-08-15

申请号：US10779503

申请日：2004-02-13

Applicant: David Arthur James Webb, Jr. ,  James Keller ,  Derrick R. Meyer

Inventor： David Arthur James Webb, Jr. ,  James Keller ,  Derrick R. Meyer

IPC: G06F9/30

CPC classification number: G06F7/76 ,  G06F7/4824 ,  G06F7/508 ,  G06F7/535 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F2207/5352

Abstract: A method and apparatus to allow program steps in an issue queue to be sent to the execution queue in a non program order provides reduced stall by allowing out of program order steps to be executed as needed resources become available. The method uses a modulus operation to preassign locations in the execution queues, and keep the entries in proper program order. The method employs an additional bit to represent the modules result (value) and may also utilize a load store number mapping memory to increase execution speed. With such an arrangement a computer system may decrease the lost performance due to waiting for required resource (i.e., memory or bus) availability for the current instruction, by issuing instructions for which the memory or bus resource is available even though the instruction is not the next one in the original program order. Thus the present invention allows memory reference instructions to issue as resources are available.

Abstract translation: 允许以非程序顺序将发布队列中的程序步骤发送到执行队列的方法和装置通过允许在需要的资源变得可用时执行程序顺序步骤来减少停止。 该方法使用模数运算来对执行队列中的位置进行预分配，并使条目保持正确的程序顺序。 该方法使用附加位来表示模块结果（值），并且还可以利用加载存储器号映射存储器来增加执行速度。 通过这样的布置，由于等待当前指令的所需资源（即，存储器或总线）可用性，计算机系统可以通过发出存储器或总线资源可用的指令来减少丢失的性能，即使该指令不是 下一个在原程序中。 因此，本发明允许存储器参考指令在资源可用时发布。

公开(公告)号：US06738896B1

公开(公告)日：2004-05-18

申请号：US09495190

申请日：2000-01-31

Applicant: David Arthur James Webb, Jr. ,  James Keller ,  Derrick R. Meyer

Inventor： David Arthur James Webb, Jr. ,  James Keller ,  Derrick R. Meyer

IPC: G06F930

CPC classification number: G06F7/76 ,  G06F7/4824 ,  G06F7/508 ,  G06F7/535 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F2207/5352

Abstract: A method and apparatus to allow program steps in an issue queue to be sent to the execution queue in a non program order provides reduced stall by allowing out of program order steps to be executed as needed resources become available. The method uses a modulus operation to preassign locations in the execution queues, and keep the entries in proper program order. The method employs an additional bit to represent the modules result (valve) and may also utilize a load store number mapping memory to increase execution speed. With such an arrangement a computer system may decrease the lost performance due to waiting for required resource (i.e., memory or bus) availability for the current instruction, by issuing instructions for which the memory or bus resource is available even though the instruction is not the next one in the original program order. Thus the present invention allows memory reference instructions to issue as resources are available.

Abstract translation: 允许以非程序顺序将发布队列中的程序步骤发送到执行队列的方法和装置通过允许在需要的资源变得可用时执行程序顺序步骤来减少停止。 该方法使用模数运算来对执行队列中的位置进行预分配，并使条目保持正确的程序顺序。 该方法使用额外的位来表示模块结果（阀），并且还可以利用加载存储器号码映射存储器来增加执行速度。 通过这样的布置，由于等待当前指令的所需资源（即存储器或总线）可用性，计算机系统可以通过发出存储器或总线资源可用的指令来减少丢失的性能，即使该指令不是 下一个在原程序中。 因此，本发明允许存储器参考指令在资源可用时发布。

公开(公告)号：US06360314B1

公开(公告)日：2002-03-19

申请号：US09115186

申请日：1998-07-14

Applicant: David Arthur James Webb, Jr. ,  James B. Keller ,  Derrick R. Meyer

Inventor： David Arthur James Webb, Jr. ,  James B. Keller ,  Derrick R. Meyer

IPC: G06F938

CPC classification number: G06F9/3834 ,  G06F9/3826

Abstract: A bypass mechanism is disclosed for a computer system that executes load and store instructions out of order. The bypass mechanism compares the address of each issuing load instruction with a set of recent store instructions that have not yet updated memory. A match of the recent stores provides the load data instead of having to retrieve the data from memory. A store queue holds the recently issued stores. Each store queue entry and the issuing load includes a data size indicator. Subsequent to a data bypass, the data size indicator of the issuing load is compared against the data size indicator of the matching store queue entry. A trap is signaled when the data size indicator of the issuing load differs from the data size indicator of the matching store queue entry. The trap signal indicates that the data provided by the bypass mechanism was insufficient to satisfy the requirements of the load instruction. The bypass mechanism also operates in cases in which multiple prior stores to the same address are pending when a load that needs to read that address issues.

Abstract translation: 公开了一种用于执行装载和存储指令的计算机系统的旁路机构。 旁路机制将每个发布加载指令的地址与尚未更新内存的一组最近的存储指令进行比较。 最近的商店的匹配提供了加载数据，而不是从内存中检索数据。 商店队列持有最近发布的商店。 每个存储队列条目和发布加载包括数据大小指示符。 在数据旁路之后，将发布负载的数据大小指示符与匹配存储队列条目的数据大小指示符进行比较。 当发布负载的数据大小指示符与匹配的存储队列条目的数据大小指示符不同时，用信号通知陷阱。 陷阱信号表示旁路机构提供的数据不足以满足加载指令的要求。 在需要读取该地址的负载发生问题的情况下，旁路机制还可以在多个先前存储到同一地址的情况下进行操作。

公开(公告)号：US07100096B2

公开(公告)日：2006-08-29

申请号：US10675133

申请日：2003-09-30

Applicant: David Arthur James Webb, Jr. ,  Richard E. Kessler ,  Steve Lang

Inventor： David Arthur James Webb, Jr. ,  Richard E. Kessler ,  Steve Lang

IPC: G06F11/00

CPC classification number: G06F11/0763 ,  G06F11/0724

Abstract: A multi-processor system in which each processor receives a message from another processor in the system. The message may contain corrupted data that was corrupted during transmission from the preceding processor. Upon receiving the message, the processor detects that a portion of the message contains corrupted data. The processor then replaces the corrupted portion with a predetermined bit pattern known or otherwise programmed into all other processors in the system. The predetermined bit pattern indicates that the associated portion of data was corrupted. The processor that detects the error in the message preferably alerts the system that an error has been detected. The message now containing the predetermined bit pattern in place of the corrupted data is retransmitted to another processor. The predetermined bit pattern will indicate that an error in the message was detected by the previous processor. In response, the processor detecting the predetermined bit pattern preferably will not alert the system of the existence of an error. The same message with the predetermined bit pattern can be retransmitted to other processors which also will detect the presence of the predetermined bit pattern and in response not alert the system of the presence of an error. As such, because only the first processor to detect an error alerts the system of the error and because messages containing uncorrectable errors still are transmitted through the system, fault isolation is improved and the system is less likely to fall into a deadlock condition.

公开(公告)号：US06374344B1

公开(公告)日：2002-04-16

申请号：US09200248

申请日：1998-11-25

Applicant: David Arthur James Webb, Jr. ,  James B. Keller ,  Derrick R. Meyer

Inventor： David Arthur James Webb, Jr. ,  James B. Keller ,  Derrick R. Meyer

IPC: G06F1208

CPC classification number: G06F12/0859

Abstract: A technique handles load instructions within a data processor that includes a cache circuit having a data cache and a tag memory indicating valid entries within the data cache. The technique involves writing data to the data cache during a series of four processor cycles in response to a first load instruction. Additionally, the technique involves updating the tag memory and preventing reading of the tag memory in response to the first load instruction during a first processor cycle in the series of processor cycles. Furthermore, the technique involves reading tag information from the tag memory during a processor cycle of the series of four processor cycles following the first processor cycle in response to a second load instruction.

Abstract translation: 一种技术处理数据处理器内的加载指令，该数据处理器包括具有数据高速缓存的高速缓冲存储器和指示数据高速缓存内的有效条目的标签存储器。 该技术涉及在响应于第一加载指令的四个处理器周期的一系列期间将数据写入数据高速缓存。 此外，该技术涉及在一系列处理器周期中的第一处理器周期期间响应于第一加载指令更新标签存储器并防止标签存储器的读取。 此外，该技术涉及在响应于第二加载指令的第一处理器周期之后的四个处理器周期的系列的处理器周期期间从标签存储器读取标签信息。

公开(公告)号：US6154828A

公开(公告)日：2000-11-28

申请号：US072632

申请日：1993-06-03

Applicant: Joseph Dominic Macri ,  Francis X. McKeen ,  Joel S. Emer ,  William Robert Grundmann ,  Robert P. Nix ,  David Arthur James Webb, Jr.

Inventor： Joseph Dominic Macri ,  Francis X. McKeen ,  Joel S. Emer ,  William Robert Grundmann ,  Robert P. Nix ,  David Arthur James Webb, Jr.

IPC: G06F9/38

CPC classification number: G06F9/3853 ,  G06F9/3836 ,  G06F9/3838

Abstract: A method and apparatus including means for storing an executable file which includes a group of bits which define functional operations and cycle bits associated with each functional operation and means for completing a variable number of the functional operations in parallel during a single execution cycle in accordance with a state of the associated cycle bit. The method and apparatus eliminates the need for complex data dependency checking hardware and allows a minimum amount of control logic to complete execution of executable files. The method and apparatus further minimizes the necessity of adding null operations (NOPs) to executable files which reduces the amount of storage space necessary to store the executable files and allows executable files to be used on multiple hardware implementations and for register values to be used for multiple purposes during single execution cycles.

Abstract translation: 一种方法和装置，包括用于存储可执行文件的装置，该可执行文件包括定义与每个功能操作相关联的功能操作和周期位的一组比特，以及用于在单个执行周期期间根据单个执行周期并行地完成可变数量的功能操作的装置 相关联的周期位的状态。 该方法和装置消除了对复杂数据依赖性检查硬件的需要，并允许最小量的控制逻辑来完成可执行文件的执行。 该方法和装置进一步最小化了对可执行文件添加空操作（NOP）的必要性，这减少了存储可执行文件所需的存储空间量，并允许在多个硬件实现上使用可执行文件，并且使用用于 在单个执行周期中有多个目的。