公开(公告)号：US06317847B1

公开(公告)日：2001-11-13

申请号：US09144644

申请日：1998-08-31

Applicant: Pierre F. Haubursin ,  Ching Yu ,  Din-I Tsai ,  David Balmforth

Inventor： Pierre F. Haubursin ,  Ching Yu ,  Din-I Tsai ,  David Balmforth

IPC: G06F1100

CPC classification number: G06F11/3636 ,  G06F11/3466 ,  G06F11/3648

Abstract: A system for tracing read and write accesses to selected registers is provided in a network interface. The system has a read trace register containing a separate bit for each register to be monitored for read access by an external CPU. A write trace register is provided with a bit for each register to be monitored for write access by the CPU. When the CPU performs read or write access to a monitored register, a decoder that decodes an address signal from the CPU produces a trace select signal supplied to the read trace register and/or write trace register. In response to the trace select signal, the bit representing the monitored register is set to a predetermined logic state indicating that the monitored register was accessed by the CPU for reading and/or writing.

Abstract translation: 在网络接口中提供了用于跟踪对所选寄存器的读和写访问的系统。 该系统具有一个读取跟踪寄存器，每个寄存器包含一个独立的位，用于监视外部CPU进行读取访问。 写入跟踪寄存器为每个待监视的寄存器提供一个位，以便CPU进行写访问。 当CPU对被监视的寄存器执行读或写访问时，从CPU解码地址信号的解码器产生提供给读跟踪寄存器和/或写跟踪寄存器的跟踪选择信号。 响应于跟踪选择信号，表示被监视寄存器的位被设置为预定的逻辑状态，指示所监视的寄存器被CPU访问以用于读取和/或写入。