公开(公告)号：US07694163B1

公开(公告)日：2010-04-06

申请号：US11610623

申请日：2006-12-14

Applicant: David C. Bisbee

Inventor： David C. Bisbee

IPC: G06F1/26

CPC classification number: G06F1/189

Abstract: A system for generating and monitoring voltages on a variety of different components on a common printed circuit board. The system includes a programmable controller, a plurality of DC/DC converters for producing voltages for the devices and a plurality of voltage regulators for produced voltages for a plurality of CPUs on the board, such CPU voltages being produced in accordance with VIDs provided to the regulator by the CPU. The programmable controller: establishes a set point voltage for such one of the DC/DC converters; sequentially monitors the produced voltages produced, monitors voltages produced by the regulators for the CPUs by comparing the VIDs to the voltages produced by the regulators, and if during the sequencing any one of the converters is determined by the programmable controller as producing an improper voltage or if the any one of the regulators fails top produce the voltage indicated by the VIDs, disables the board.

Abstract translation: 用于在通用印刷电路板上的各种不同部件上产生和监测电压的系统。 该系统包括可编程控制器，用于为器件产生电压的多个DC / DC转换器和用于板上多个CPU的产生电压的多个稳压器，这些CPU电压根据提供给 由CPU调节。 可编程控制器：为DC / DC转换器之一建立一个设定点电压; 通过将VID与调节器产生的电压进行比较来监控所产生的所产生的电压，监视由调节器产生的电压，并且如果在排序期间，任何一个转换器由可编程控制器确定为产生不正确的电压或 如果任何一个稳压器故障顶部产生VID所示的电压，则禁用该板。

公开(公告)号：US07062620B1

公开(公告)日：2006-06-13

申请号：US10331423

申请日：2002-12-30

Applicant: David C. Bisbee ,  Scot C. Tata ,  Erik C. Nelson ,  Thomas Delucia ,  Thomas E. Linnell ,  William R. Tuccio ,  Edward J. Claprood ,  Enrico DiFabio ,  Brian Gallagher ,  Lawrence G. Pignolet

Inventor： David C. Bisbee ,  Scot C. Tata ,  Erik C. Nelson ,  Thomas Delucia ,  Thomas E. Linnell ,  William R. Tuccio ,  Edward J. Claprood ,  Enrico DiFabio ,  Brian Gallagher ,  Lawrence G. Pignolet

IPC: G00F12/00

CPC classification number: G06F12/0866

Abstract: A data storage interface for coupling data between processors and a bank of disk. The interface includes a plurality of first directors coupled to the processors and a plurality of second directors coupled to the bank of disk drives. A cache memory is coupled between the plurality of first directors and the plurality of second directors. The interface includes a pair of independent power busses. At least one of the first or second directors is coupled to the pair of independent power busses. One portion of the disk drives in the bank is connected to only a first one of the pair of power buses and a different portion of the disk drives is connected to only the other one of the pair of power buses. A power circuit includes a pair of input terminals, each one being electrically connected to a corresponding one of the pair of independent power busses. The circuit includes an output terminal. A pair of switching transistor sections is provided. The transistor switching sections is serially connected between a corresponding one of the pair of input terminals and the output terminal. A logic network is provided for operating the switching sections to prevent current passing into one of the pair of input terminals from one of the power busses from passing into the other one of the power buses. The logic section operates the switching sections to prevent current from one of the pair of power buses to the one of the input terminals connected thereto from exceeding a predetermined value, and operates the switching sections to prevent a difference between a voltage at one of the input terminals and a voltage at the other one of the input terminals from exceeding a predetermined value.

Abstract translation: 一种数据存储接口，用于在处理器和一组磁盘之间耦合数据。 接口包括耦合到处理器的多个第一引导器和耦合到盘驱动器组的多个第二引导器。 高速缓冲存储器耦合在多个第一引导器和多个第二引导器之间。 该接口包括一对独立的电力总线。 第一或第二导体中的至少一个耦合到一对独立电力总线。 组中的磁盘驱动器的一部分仅连接到一对电源总线中的第一个，并且磁盘驱动器的不同部分仅连接到该对电源总线中的另一个。 电源电路包括一对输入端子，每一个输入端子电连接到该对独立电力总线中相应的一个。 该电路包括输出端子。 提供一对开关晶体管部分。 晶体管开关部串联连接在一对输入端子和输出端子的对应的一个。 提供了一个逻辑网络，用于操作开关部分，以防止电流从一个电力总线进入一对输入端子中的一个，以进入另一个电力总线。 逻辑部分操作切换部分，以防止从一对电力总线中的一个到连接到其上的一个输入端子的电流超过预定值，并且操作开关部分以防止输入之一处的电压之间的差 端子和另一个输入端子处的电压超过预定值。