公开(公告)号：US20150098540A1

公开(公告)日：2015-04-09

申请号：US14373924

申请日：2012-02-24

申请人： Michael Priel ,  David Dzebisashvili ,  Leonid Fleshel

发明人： Michael Priel ,  David Dzebisashvili ,  Leonid Fleshel

IPC分类号： H04L25/45 ,  H04L25/44

CPC分类号： H04L25/45 ,  G06F1/10 ,  H04L25/44

摘要： A clock distribution module for a digital synchronous system is described. The clock distribution module comprising a first node arranged to comprise a clock signal comprising a propagation delay relative to a reference clock signal, at least one further node arranged to comprise a clock signal comprising a propagation delay relative to the reference clock signal corresponding to that of the first node, and a clock configuration module. The clock configuration module is arranged to receive at least one indication of clock skew between the first node and at least one further node of the clock distribution module, and to selectively couple the first node to the at least one further node based at least partly on the at least one indication of clock skew there between.

摘要翻译： 描述了用于数字同步系统的时钟分配模块。 所述时钟分配模块包括被布置为包括相对于参考时钟信号的传播延迟的时钟信号的第一节点，至少一个另外的节点，被布置为包括时钟信号，该时钟信号包括相对于参考时钟信号的参考时钟信号的传播延迟 第一个节点和一个时钟配置模块。 时钟配置模块被布置成接收时钟分配模块的第一节点和至少一个另外节点之间的时钟偏移的至少一个指示，并且至少部分地基于第一节点选择性地将第一节点耦合到至少一个另外的节点 其间的时钟偏移的至少一个指示。

公开(公告)号：US09178730B2

公开(公告)日：2015-11-03

申请号：US14373924

申请日：2012-02-24

申请人： Michael Priel ,  David Dzebisashvili ,  Leonid Fleshel

发明人： Michael Priel ,  David Dzebisashvili ,  Leonid Fleshel

IPC分类号： H04L7/00 ,  H04L25/45 ,  G06F1/10 ,  H04L25/44

CPC分类号： H04L25/45 ,  G06F1/10 ,  H04L25/44

摘要： A clock distribution module for a digital synchronous system is described. The clock distribution module comprising a first node arranged to comprise a clock signal comprising a propagation delay relative to a reference clock signal, at least one further node arranged to comprise a clock signal comprising a propagation delay relative to the reference clock signal corresponding to that of the first node, and a clock configuration module. The clock configuration module is arranged to receive at least one indication of clock skew between the first node and at least one further node of the clock distribution module, and to selectively couple the first node to the at least one further node based at least partly on the at least one indication of clock skew there between.

摘要翻译： 描述了用于数字同步系统的时钟分配模块。 所述时钟分配模块包括被布置为包括相对于参考时钟信号的传播延迟的时钟信号的第一节点，至少一个另外的节点，被布置为包括时钟信号，该时钟信号包括相对于参考时钟信号的参考时钟信号的传播延迟 第一个节点和一个时钟配置模块。 时钟配置模块被布置成接收时钟分配模块的第一节点和至少一个另外节点之间的时钟偏移的至少一个指示，并且至少部分地基于第一节点选择性地将第一节点耦合到至少一个另外的节点 其间的时钟偏移的至少一个指示。