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公开(公告)号：US08965304B2
公开(公告)日：2015-02-24
申请号：US12380092
申请日：2009-02-23
IPC分类号： H04B1/44 , H03K19/0175 , H04L25/02 , H04L25/45
CPC分类号： H04L25/0272 , H01L2224/48091 , H01L2224/49175 , H01L2924/13091 , H01L2924/30107 , H01L2924/3011 , H04L25/0264 , H04L25/0282 , H04L25/0294 , H04L25/45 , H01L2924/00014 , H01L2924/00
摘要： A multi-mode I/O circuit or cell (10) is provided for transmitting and receiving data between ICs, where each IC contains at least one of the I/O circuits. Each data link includes transmitter circuitry (12) and receiver circuitry (14). The transmitter circuitry sends data to a receiver circuitry in another IC, and the receiver circuitry receives data from a transmitter circuitry in another IC. The I/O circuit is constructed with CMOS-based transistors (e.g., CMOS or BiCMOS) that are selectively interconnected together by a plurality of switches to operate as two single-ended, current or voltage mode links, or as a single differential current or voltage mode link. In the preferred embodiment the transmitter circuitry sends data to the receiver circuitry in another IC over a first pair of adjacently disposed conductors, and the receiver circuitry receives data from the transmitter circuitry in another IC over a second pair of adjacently disposed conductors. The transmitter circuitry and the receiver circuitry are selectively configured by the plurality of switches for operating in a double single-ended voltage mode link mode, a double single-ended current mode link mode, a mode defined by a single differential voltage mode link with a single-ended input drive, a mode defined by a single differential voltage mode link with a differential input drive, a mode defined by a single differential current mode link with a single-ended input drive mode, and a mode defined by a single differential current mode link with a differential input drive. A common I/O circuit may also be provided, and programmed into either the transmitter or the receiver circuit configuration.
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2.发明申请Transmitter circuit, receiver circuit, clock data recovery phase locked loop circuit, data transfer method and data transfer system 有权发射机电路，接收机电路，时钟数据恢复锁相环电路，数据传输方式和数据传输系统公开(公告)号：US20050286643A1
公开(公告)日：2005-12-29
申请号：US11104586
申请日：2005-04-13
申请人： Seiichi Ozawa , Jun-ichi Okamura , Yohei Ishizone , Satoshi Miura
发明人： Seiichi Ozawa , Jun-ichi Okamura , Yohei Ishizone , Satoshi Miura
IPC分类号： H03D3/18 , H03K9/08 , H03L7/087 , H03L7/091 , H03L7/113 , H03M9/00 , H04B14/04 , H04L7/033 , H04L25/45 , H04L25/49 , H04N11/04
摘要： [Problems] To realize a reliable and stable transfer of digital data that does not require a reference clock and a handshake operation. [Means for Solving the Problem] The present invention provides a digital data transfer method for alternately and periodically transferring first information and second information respectively in a first period and in a second period, wherein: an amount of information of the first information per unit time in the first period is greater than an amount of information of the second information per unit time in the second period; and the second information in the first period is transferred as pulse-width-modulated serial data.
摘要翻译： [问题]实现不需要参考时钟和握手操作的数字数据的可靠而稳定的传输。 解决问题的手段本发明提供一种用于在第一周期和第二周期中分别交替地和周期性地传送第一信息和第二信息的数字数据传送方法，其中：每单位时间的第一信息的信息量 在第一期间中，比第二期间的每单位时间的第二信息的信息量大; 并且第一周期中的第二信息作为脉冲宽度调制的串行数据传送。
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公开(公告)号：US20050231232A1
公开(公告)日：2005-10-20
申请号：US11152268
申请日：2005-06-13
CPC分类号： H04L25/45
摘要： In some embodiments, a chip includes first and second nodes, a variable voltage source, and transmitter and control circuitry. The transmitter includes a driver coupled to the first and second nodes, and first and second resistive structures coupled between the first and second nodes, respectively, and the variable voltage source. The control circuitry selects an impedance level for the first and second resistive structures, and detect coupling of a remote receiver to the transmitter through interconnects and detect decoupling of the remote receiver from the transmitter. Other embodiments are described and claimed.
摘要翻译： 在一些实施例中，芯片包括第一和第二节点，可变电压源以及发射器和控制电路。 发射机包括耦合到第一和第二节点的驱动器以及分别耦合在第一和第二节点之间的第一和第二电阻结构以及可变电压源。 控制电路选择第一和第二电阻结构的阻抗水平，并通过互连检测远程接收器与发射机的耦合，并检测远端接收机与发射机的去耦合。 描述和要求保护其他实施例。
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公开(公告)号：US06931027B1
公开(公告)日：2005-08-16
申请号：US09624816
申请日：2000-07-25
申请人： Danny Vogel , Bryan Robb , Clinton Seeman
发明人： Danny Vogel , Bryan Robb , Clinton Seeman
CPC分类号： H04L25/45
摘要： In a Framed Packet Bus (FPB) serial bus, an improved protocol and circuit layout for communication between devices grounded in the same chassis or chip. The improved protocol eliminates the requirement that bits have DC balance in their HIGH and LOW voltage levels. Consequently, bus overhead is reduced over prior techniques. In one example, data capacity utilization was increased from 80% to 95% and bus overhead was reduced from 20% to 5%. As a result of increased capacity, more packets of data may be carried across the serial bus, and any leftover bits within the frame cycle and in subsequent cycles may carry error detection information or be utilized as a control for the bus. In one preferred embodiment, the FPB serial bus configuration consists of sixteen serial lines arranged in parallel.
摘要翻译： 在帧分组总线（FPB）串行总线中，改进的协议和电路布局用于在同一机箱或芯片上接地的设备之间进行通信。 改进的协议消除了在高电平和低电平电平下具有直流平衡的要求。 因此，总线开销比现有技术减少。 在一个例子中，数据容量利用率从80％提高到95％，总线开销从20％下降到5％。 作为增加容量的结果，可以在串行总线上携带更多的数据包，并且在帧周期内和随后的周期中的任何剩余位可以携带错误检测信息或用作总线的控制。 在一个优选实施例中，FPB串行总线配置由并行布置的十六个串行线组成。
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5.发明申请Method and apparatus for selectably providing single-ended and differential signaling with controllable impedance and transition time 有权用于可选择地提供具有可控阻抗和转换时间的单端和差分信号的方法和装置公开(公告)号：US20050104619A1
公开(公告)日：2005-05-19
申请号：US10952921
申请日：2004-09-30
申请人： Scott Best , Chiping Yang
发明人： Scott Best , Chiping Yang
IPC分类号： H04L25/02 , G06F13/40 , H03K5/22 , H03K17/16 , H03K19/003 , H03K19/0185 , H04L25/08 , H04L25/45 , H04Q20060101
CPC分类号： H04L25/0298 , G06F13/4072 , G06F13/4086 , H03K17/164 , H03K19/018585 , H04L25/0272 , H04L25/0278 , H04L25/028 , H04L25/085 , H04L25/45
摘要： A method and apparatus for selectably providing single-ended and differential signaling with controllable impedance and transition time is provided. According to the method and apparatus, a differential signal can be transmitted over two wires or two single-ended signals can be transmitted over the two wires. According to the method and apparatus, termination may be selected among a single-reference termination, a center termination, or a high-impedance termination. Regardless of the type of termination selected, a capability for dynamic control of the termination impedance is provided. Moreover, an ability to change impedances of termination elements to maintain a desired termination impedance for both single-reference termination and center termination modes by shifting bits is provided. Also, a capability for dynamic control of transition times of signals is provided.
摘要翻译： 提供了一种可选择地提供具有可控阻抗和转换时间的单端和差分信号的方法和装置。 根据该方法和装置，差分信号可以通过两条线路传输，或者两条单端信号可以通过两条线路传输。 根据该方法和装置，可以在单参考终端，中心终端或高阻抗终端中选择终止。 不管选择的终端类型如何，都提供了终端阻抗的动态控制能力。 此外，提供了通过移位来改变端接元件的阻抗以维持单参考端接和中心端接模式的期望的终端阻抗的能力。 此外，还提供了用于动态控制信号的转换时间的能力。
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6.发明申请公开(公告)号：US20050017783A1
公开(公告)日：2005-01-27
申请号：US10890493
申请日：2004-07-13
申请人： Jae-hyung Lee , Kyu-hyoun Kim
发明人： Jae-hyung Lee , Kyu-hyoun Kim
IPC分类号： H03K5/02 , H03K3/356 , H03K19/003 , H03K19/0185 , H04L25/02 , H04L25/45 , H03K3/037
CPC分类号： H04L25/45 , H03K3/356104 , H03K3/356113 , H03K19/00323 , H03K19/018521
摘要： Provided are an interface circuit and a signal clamping circuit using a level-down shifter. The interface circuit includes the level-down shifter between a first power circuit driven by a first power and a second power circuit driven by a second power. The level-down shifter converts an output of the first power circuit that has a voltage level of the first power into an output of a voltage level of the second power. The level-down shifter includes a first circuit unit, a second circuit unit, a third circuit unit, and a fourth circuit unit. The first circuit unit is driven by the first power and receives the output of the first power circuit. The second circuit unit is driven by the second power and receives the output of the first power circuit. The third circuit unit is driven by the second power and receives the output of the first power circuit. The fourth circuit unit is driven by the second power, receives an output of the third circuit unit, and is connected to an output of the second circuit unit.
摘要翻译： 提供了使用电平降低移位器的接口电路和信号钳位电路。 接口电路包括由第一电源驱动的第一电源电路和由第二电源驱动的第二电源电路之间的电平降低移位器。 电平降低移位器将具有第一功率的电压电平的第一电源电路的输出转换为第二功率的电压电平的输出。 电平降低移位器包括第一电路单元，第二电路单元，第三电路单元和第四电路单元。 第一电路单元由第一电源驱动并接收第一电源电路的输出。 第二电路单元由第二电源驱动并接收第一电源电路的输出。 第三电路单元由第二电源驱动并接收第一电源电路的输出。 第四电路单元由第二电源驱动，接收第三电路单元的输出，并连接到第二电路单元的输出端。
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公开(公告)号：US06845131B1
公开(公告)日：2005-01-18
申请号：US09680528
申请日：2000-10-03
CPC分类号： H04L25/14 , H04L25/0272 , H04L25/028 , H04L25/0292 , H04L25/45 , H04W52/08
摘要： For a low voltage differential signalling technology to achieve more and faster processing, minimizing power consumption is important. A method of power management is provided whereby the transmitter circuitry is powered down at appropriate times and a minimum number of active links is maintained to maintain the integrity of the state of the logic in the receiver circuitry.
摘要翻译： 对于低压差分信号技术来实现越来越快的处理，最大限度地降低功耗是很重要的。 提供了一种功率管理的方法，其中发射机电路在合适的时间被断电，并且保持最小数量的有源链路以维持接收机电路中的逻辑状态的完整性。
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公开(公告)号：US5760707A
公开(公告)日：1998-06-02
申请号：US606680
申请日：1996-02-26
申请人： Takashi Katagiri
发明人： Takashi Katagiri
摘要： In a method of transmitting multiple serial signals, parallel signals are converted into serial signals by a plural number of parallel-to-serial converters contained in a transmitter, serial signals are converted into parallel signals by a plural number of serial-to-parallel converters contained in a receiver, and multiple serial signals are transmitted between the transmitter and the receiver through a channel. In the method, for data transmission, said plural number of parallel-to-serial converters and said plural number of serial-to-parallel converters are connected in series, and the format of the serial signals on the channel, the format for the parallel-to-serial converters located preceding to the channel, and the format for the serial-to-parallel converters located succeeding to the channel are the same formats. In this case, these formats may be of the start-stop synchronization type.
摘要翻译： 在发送多个串行信号的方法中，通过包含在发送器中的多个并行 - 串行转换器将并行信号转换成串行信号，串行信号由多个串行 - 并行转换器转换成并行信号 包含在接收机中，并且多个串行信号通过信道在发射机和接收机之间传输。 在该方法中，对于数据传输，所述多个并行到串行转换器和所述多个串并转换器串联连接，并且通道上串行信号的格式，并行格式 到串行转换器，并且位于通道后面的串行到并行转换器的格式是相同的格式。 在这种情况下，这些格式可以是起始 - 停止同步类型。
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9.发明授权Interface unit for communication device with parts positioned on a printed-wiring board for achieving desirable operating characteristics 失效用于通信设备的接口单元，其具有位于印刷电路板上的部件，以实现期望的操作特性
公开(公告)号：US5719747A
公开(公告)日：1998-02-17
申请号：US431976
申请日：1995-05-01
申请人： Kazuaki Kashiwada , Kenji Joukou , Akihiko Oka
发明人： Kazuaki Kashiwada , Kenji Joukou , Akihiko Oka
摘要： An interface unit having a digital hierarchy interface function for a communication device has parts disposed on a printed-wiring board in a Layout to maintain desired interface unit characteristics. The interface unit includes a plurality of parallel B/U converter blocks for converting bipolar signals in a plurality of channels into a plurality of unipolar signals, respectively, a plurality of parallel U/B converter blocks for converting unipolar signals in a plurality of channels into a plurality of bipolar signals, respectively, a connector disposed near the B/U converter blocks for connecting the B/U converter blocks to an external device, a shared processor LSI circuit connected to the B/U converter blocks and the U/B converter blocks and disposed near the U/B converter blocks, for interfacing the signals in the channels at a low speed, and a printed-wiring board supporting the B/U converter blocks, the U/B converter blocks, the connector, and the shared processor LSI circuit.
摘要翻译： 具有用于通信设备的数字层级接口功能的接口单元具有布置在印刷电路板上的部件，以保持期望的接口单元特性。 接口单元包括用于将多个通道中的双极性信号分别转换为多个单极信号的多个并行B / U转换器模块，用于将多个通道中的单极信号转换成多个并行U / B转换器模块的多个并行U / B转换器模块 多个双极信号，分别设置在用于将B / U转换器模块连接到外部装置的B / U转换器模块附近的连接器，连接到B / U转换器模块和U / B转换器的共享处理器LSI电路 块和放置在U / B转换器块附近，用于以低速接口通道中的信号，以及支持B / U转换器块的印刷电路板，U / B转换器块，连接器和共享 处理器LSI电路。
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公开(公告)号：US5223832A
公开(公告)日：1993-06-29
申请号：US950969
申请日：1992-09-23
申请人： Ryuji Ishida
发明人： Ryuji Ishida
IPC分类号： H04L25/45
CPC分类号： H04L25/45
摘要： A serial data transmission circuit for performing a data transmission in a serial form includes a data shift signal input terminal, a data latch signal input terminal, and an output selector, the output of which is connected to a serial data output terminal. A shift register is connected at its serial input to a serial data input terminal and at a part of its parallel outputs to the input of the selector. A barrel shifter is provided, connected at its input to the parallel outputs of the shift register. The circuit further includes a first data latch, the input of which is connected to the output of the barrel shifter, and a second data latch, the output of which is connected to the parallel inputs of the shift register. The output of the first data latch is connected to the input of the second data latch through an internal data bus. The serial data transmission circuit can output the serial data inputted in the state as inputted, in synchronization with the data shift signal, without an internal data transfer being effected by the selection of an appropriate parallel output from the shift register through the output selector and also by masking of the data latch signal.
摘要翻译： 用于以串行形式执行数据传输的串行数据传输电路包括数据移位信号输入端，数据锁存信号输入端和输出选择器，其输出端连接到串行数据输出端。 移位寄存器在其串行输入端连接到串行数据输入端，并将其并行输出的一部分连接到选择器的输入端。 提供桶形移位器，其输入端连接到移位寄存器的并行输出端。 电路还包括第一数据锁存器，其输入端连接到桶形移位器的输出端，第二数据锁存器输出连接到移位寄存器的并行输入端。 第一数据锁存器的输出通过内部数据总线连接到第二数据锁存器的输入端。 串行数据传输电路可以与数据移位信号同步地输出输入状态的串行数据，而无需通过输出选择器从移位寄存器中选择合适的并行输出来实现内部数据传输，而且 通过屏蔽数据锁存信号。
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