公开(公告)号：US5278467A

公开(公告)日：1994-01-11

申请号：US913447

申请日：1992-07-14

申请人： David J. Nedwek

发明人： David J. Nedwek

IPC分类号： H03K5/02 ,  H03K5/24 ,  H03K5/153 ,  H03K3/26

CPC分类号： H03K5/2481 ,  H03K5/023

摘要： A circuit that includes a self-biased differential amplifier a level restore circuit. The output of the differential amplifier is coupled to the source pins of a p type transistor and an n type transistor. The output of the differential amplifier is further coupled to a first inverter circuit that provides feedback to the gates of the p and n type transistors. The first inverter also further amplifies the output voltage of the differential amplifier. When the differential amplifier outputs a high voltage, the p transistor attempts to drain the output and pull the output voltage down. When the differential amplifier begins switching from a high voltage to a low voltage, the p transistor accelerates the voltage swing and decreases the propagation delay of the buffer circuit. Likewise, when the differential amplifier swings from a low voltage to a high voltage, the n type transistor reduces the propagation delay of the voltage swing.

摘要翻译： 一种包括自偏置差分放大器电平恢复电路的电路。 差分放大器的输出端耦合到p型晶体管和n型晶体管的源极引脚。 差分放大器的输出进一步耦合到向p型和n型晶体管的栅极提供反馈的第一反相器电路。 第一个反相器还进一步放大差分放大器的输出电压。 当差分放大器输出高电压时，p晶体管尝试耗尽输出并将输出电压拉低。 当差分放大器开始从高电压切换到低电压时，p晶体管加速电压摆幅并减小缓冲电路的传播延迟。 同样，当差分放大器从低电压摆动到高电压时，n型晶体管减小了电压摆幅的传播延迟。

公开(公告)号：US5701420A

公开(公告)日：1997-12-23

申请号：US744123

申请日：1996-11-05

申请人： David J. Nedwek ,  Howard Wilson ,  Steve Nugent ,  Greg Dermer

发明人： David J. Nedwek ,  Howard Wilson ,  Steve Nugent ,  Greg Dermer

IPC分类号： G06F15/173 ,  G06F15/16

CPC分类号： G06F15/17343

摘要： A method for configuring a plurality of configurable components within a computer system. The method includes the step of asserting a RESET signal for all of the configurable components. The RESET signal is asserted by a diagnostic processor within the system. The components each respond with an ERROR # signal which provides an indication to the diagnostic processor that the component is in an inactive state. After a predetermined number of clock signals the diagnostic processor configures a first component, then a second component and so forth and so on, until all of the components are configured. After all of the components are configured, the diagnostic processor deasserts the RESET signal for the first component, then deasserts the RESET signal for the second component and so forth and so on, until all of the RESET signals have been deasserted. Each component deasserts the ERROR # signal upon the deassertion of the RESET signal. The diagnostic processor allows normal operation to occur upon the deassertion of all the ERROR # signals.

摘要翻译： 一种用于在计算机系统内配置多个可配置组件的方法。 该方法包括为所有可配置组件确定RESET信号的步骤。 RESET信号由系统内的诊断处理器确定。 每个组件以ERROR＃信号进行响应，该信号向诊断处理器提供组件处于非活动状态的指示。 在预定数量的时钟信号之后，诊断处理器配置第一组件，然后配置第二组件等等，直到配置所有组件。 在配置了所有组件之后，诊断处理器将第一个组件的RESET信号置为无效，然后取消对第二个组件的RESET信号等等，直到所有的RESET信号都被置为无效。 每个组件在RESET信号的取消状态时取消断开ERROR＃信号。 诊断处理器允许正常操作发生在所有ERROR＃信号消除时。

公开(公告)号：US5355504A

公开(公告)日：1994-10-11

申请号：US794467

申请日：1991-11-19

申请人： David J. Nedwek

发明人： David J. Nedwek

IPC分类号： G06F15/80 ,  G06F15/00

CPC分类号： G06F15/8023 ,  G06F15/8007

摘要： A system for enabling processor cells in a high speed multi-processor environment to communicate with each other so as to resolve synchronization problems caused by propagation and other delays inherent in such an environment. The invention is for systems for which the data delay is both bounded and fixed wherein the maximum data delay is part of the system specifications and all cells operate at the same frequency. Data is transmitted along with a clock to allow the receiving cell to properly recover the data regardless of the state of the receiver's internal clocks. Both the transmitting cell and the receiving cell are operating at the same frequency (because their clock signals are derived from the same master oscillator), but the range of delays associated with the transmission of data places no bounds on the allowable phase difference between the received data's clock and the receiver's internal clock state.

摘要翻译： 用于使高速多处理器环境中的处理器单元能够彼此通信的系统，以便解决由这种环境中固有的传播和其他延迟引起的同步问题。 本发明适用于数据延迟有界和固定的系统，其中最大数据延迟是系统规范的一部分，并且所有单元以相同的频率工作。 数据与时钟一起发送，以允许接收单元正确地恢复数据，而不管接收机的内部时钟的状态如何。 发射小区和接收小区都以相同的频率工作（因为它们的时钟信号是从相同的主振荡器导出的），而与数据传输相关的延迟范围对接收到的允许的相位差没有限制 数据的时钟和接收机的内部时钟状态。