公开(公告)号：US08891267B2

公开(公告)日：2014-11-18

申请号：US13819968

申请日：2011-08-31

申请人： Paul Bourne ,  Philip Tracy ,  David Murfett

发明人： Paul Bourne ,  Philip Tracy ,  David Murfett

IPC分类号： H02M7/04 ,  G05F3/16 ,  H02M7/12 ,  H02M7/217 ,  H02M1/00

CPC分类号： H02M7/125 ,  H02M7/217 ,  H02M7/2176 ,  H02M2001/0032 ,  Y02B70/16

摘要： A circuit arrangement with standby mode minimizing power and/or current consumption having a mains AC power supply terminals and an active circuit capable of converting said mains AC power to lower voltage DC levels for operating in an active mode or in a standby mode as required by an appliance such that the selection of the current sensing resistor value for said current sensing resistor limits the maximum peak current through the FET so that the current sensing resistor arrangement is capable of providing significant increases in a steeper rise time of the current at around mains AC power supply zero crossing, so that current is pulled high while the mains AC power supply voltage is low.

摘要翻译： 具有待机模式的电路装置使功率和/或电流消耗最小化具有市电AC电源端子和能够将所述市电AC功率转换成较低电压DC电平的有源电路，用于以活动模式或待机模式操作，如 一种用于所述电流感测电阻器的电流感测电阻器值的选择限制了通过FET的最大峰值电流，使得电流感测电阻器装置能够显着提高在电源AC周围的电流的更陡峭的上升时间 电源过零，使电流拉高，而市电交流电源电压低。

公开(公告)号：US07840734B2

公开(公告)日：2010-11-23

申请号：US11960152

申请日：2007-12-19

申请人： David Murfett ,  Paul Bourne ,  Philip Tracy

发明人： David Murfett ,  Paul Bourne ,  Philip Tracy

IPC分类号： G06F13/00

CPC分类号： G06F13/4077

摘要： A bus buffer can include a data buffer and a clock signal buffer. The data buffer for can include two symmetrical buffer circuits with an output signal that can follow the input voltage to provide bi-directional buffer action for a data path of the bus buffer. The clock buffer can operate in a forward or reverse direction, where the signal direction for the clock signal path in the bus buffer can be controlled with a direction input. The bus buffer can also include an enable circuit for enabling the data path and the clock signal path.

摘要翻译： 总线缓冲器可以包括数据缓冲器和时钟信号缓冲器。 数据缓冲器可以包括两个具有输出信号的对称缓冲器电路，输出信号可以跟随输入电压，为总线缓冲器的数据通路提供双向缓冲器动作。 时钟缓冲器可以在正向或反向工作，其中可以通过方向输入来控制总线缓冲器中的时钟信号路径的信号方向。 总线缓冲器还可以包括用于启用数据路径和时钟信号路径的使能电路。

公开(公告)号：US20130201735A1

公开(公告)日：2013-08-08

申请号：US13819968

申请日：2011-08-31

申请人： Paul Bourne ,  Philip Tracy ,  David Murfett

发明人： Paul Bourne ,  Philip Tracy ,  David Murfett

IPC分类号： H02M7/12 ,  H02M7/217

CPC分类号： H02M7/125 ,  H02M7/217 ,  H02M7/2176 ,  H02M2001/0032 ,  Y02B70/16

摘要： A circuit arrangement with standby mode minimising power and/or current consumption having a mains AC power supply terminals and an active circuit capable of converting said mains AC power to lower voltage DC levels for operating in an active mode or in a standby mode as required by an appliance such that the selection of the current sensing resistor value for said current sensing resistor limits the maximum peak current through the FET so that the current sensing resistor arrangement is capable of providing significant increases in a steeper rise time of the current at around mains AC power supply zero crossing, so that current is pulled high while the mains AC power supply voltage is low.

摘要翻译： 具有待机模式的电路装置使功率和/或电流消耗最小化具有市电AC电源端子和能够将所述市电AC功率转换成较低电压DC电平的有源电路，用于以活动模式或待机模式操作，如 一种用于所述电流感测电阻器的电流感测电阻器值的选择限制了通过FET的最大峰值电流，使得电流感测电阻器装置能够显着提高在电源AC周围的电流的更陡峭的上升时间 电源过零，使电流拉高，而市电交流电源电压低。

公开(公告)号：US20060290381A1

公开(公告)日：2006-12-28

申请号：US11426188

申请日：2006-06-23

申请人： Thi Bui ,  Malcolm Kay ,  David Murfett ,  Mark Potter ,  John Crawford

发明人： Thi Bui ,  Malcolm Kay ,  David Murfett ,  Mark Potter ,  John Crawford

IPC分类号： H03K19/0175

CPC分类号： G06F13/4072

摘要： A bi-directional bus buffer for applications using the I2C and SMBus, or other bus systems operating on similar principles, able to extend the bus load limit by buffering both the SCL and SDA (clock and data) lines, allowing capacitive loads of up to the limit of 400 pF on both sides of the buffer. With the use of an enable function, sections of the bus can be isolated, and then, thorough the use of a number of these buffers, different parts of the system are able to be isolated, and brought on-line successively or in a controlled manner, permitting a controlled start-up, and operation at maximum performance speeds while still having a diverse range of components, operating speeds and loads.

摘要翻译： 用于使用I2C和SMBus或其他以类似原理运行的总线系统的应用的双向总线缓冲器能够通过缓冲SCL和SDA（时钟和数据）线来扩展总线负载限制，允许容量负载达到 缓冲区两边400 pF的极限。 通过使用启用功能，总线的部分可以隔离，然后通过使用多个这些缓冲区，系统的不同部分能够被隔离，并连续上线或被控制 方式，允许控制启动和最大性能运行，同时仍具有不同范围的组件，运行速度和负载。

公开(公告)号：US20080183919A1

公开(公告)日：2008-07-31

申请号：US11960152

申请日：2007-12-19

申请人： Paul Bourne ,  David Murfett ,  Philip Tracy ,  Kay Malcolm ,  Potter Mark ,  Crawford John

发明人： Paul Bourne ,  David Murfett ,  Philip Tracy ,  Kay Malcolm ,  Potter Mark ,  Crawford John

IPC分类号： G06F3/00

CPC分类号： G06F13/4077

摘要： A bus buffer can include a data buffer and a clock signal buffer. The data buffer for can include two symmetrical buffer circuits with an output signal that can follow the input voltage to provide bi-directional buffer action for a data path of the bus buffer. The clock buffer can operate in a forward or reverse direction, where the signal direction for the clock signal path in the bus buffer can be controlled with a direction input. The bus buffer can also include an enable circuit for enabling the data path and the clock signal path.

摘要翻译： 总线缓冲器可以包括数据缓冲器和时钟信号缓冲器。 数据缓冲器可以包括两个具有输出信号的对称缓冲器电路，输出信号可以跟随输入电压，为总线缓冲器的数据通路提供双向缓冲器动作。 时钟缓冲器可以在正向或反向工作，其中可以通过方向输入来控制总线缓冲器中的时钟信号路径的信号方向。 总线缓冲器还可以包括用于启用数据路径和时钟信号路径的使能电路。

公开(公告)号：US07348803B2

公开(公告)日：2008-03-25

申请号：US11426188

申请日：2006-06-23

申请人： Thi Bui ,  Malcolm Kay ,  David Murfett ,  Mark Potter ,  John Crawford

发明人： Thi Bui ,  Malcolm Kay ,  David Murfett ,  Mark Potter ,  John Crawford

IPC分类号： H03K19/0175

CPC分类号： G06F13/4072

摘要： A bi-directional bus buffer for applications using the I2C and SMBus, or other bus systems operating on similar principles, able to extend the bus load limit by buffering both the SCL and SDA (clock and data) lines, allowing capacitive loads of up to the limit of 400 pF on both sides of the buffer. With the use of an enable function, sections of the bus can be isolated, and then, thorough the use of a number of these buffers, different parts of the system are able to be isolated, and brought on-line successively or in a controlled manner, permitting a controlled start-up, and operation at maximum performance speeds while still having a diverse range of components, operating speeds and loads.

摘要翻译： 用于使用I2C和SMBus或其他以类似原理运行的总线系统的应用的双向总线缓冲器能够通过缓冲SCL和SDA（时钟和数据）线来扩展总线负载限制，允许容量负载达到 缓冲区两边400 pF的极限。 通过使用启用功能，总线的部分可以隔离，然后通过使用多个这些缓冲区，系统的不同部分能够被隔离，并连续上线或被控制 方式，允许控制启动和最大性能运行，同时仍具有不同范围的组件，运行速度和负载。