公开(公告)号：US4156860A

公开(公告)日：1979-05-29

申请号：US821421

申请日：1977-08-03

Applicant: Ali E. Atia ,  David Perlmutter ,  Paul R. Schrantz

Inventor： Ali E. Atia ,  David Perlmutter ,  Paul R. Schrantz

IPC: H01P1/30 ,  H01P7/06 ,  H01P1/16

CPC classification number: H01P7/06 ,  H01P1/30

Abstract: A device for a resonant microwave cavity which includes a tuning plunger assembly to make the resonant frequency less temperature sensitive. The frequency response of a cavity filter, determined by its resonant frequency, primarily depends on the dimensions of the filter cavity. Since cavity dimensions will vary with changes in ambient temperature, some form of compensation is necessary to stabilize the frequency response. The tuning plunger assembly is comprised of a sandwich of materials having substantially different coefficients of expansion. One of the materials, a potting compound with a high coefficient of thermal expansion, acts as an operator to vary the configuration of the plunger assembly in order to maintain the resonant frequency of the cavity substantially fixed.

Abstract translation: 一种用于谐振微波腔的装置，其包括调谐柱塞组件，以使谐振频率对温度敏感。 由其谐振频率确定的腔体滤波器的频率响应主要取决于滤波器腔体的尺寸。 由于腔尺寸随环境温度的变化而变化，所以需要某种形式的补偿来稳定频率响应。 调谐柱塞组件由具有基本上不同的膨胀系数的材料夹层构成。 其中一种材料是具有高热膨胀系数的灌封化合物，用作操作者以改变柱塞组件的构型，以便保持空腔的共振频率基本上固定。

公开(公告)号：US5717898A

公开(公告)日：1998-02-10

申请号：US438615

申请日：1995-05-10

Applicant: Michael Kagan ,  David Perlmutter

Inventor： Michael Kagan ,  David Perlmutter

IPC: G06F12/08 ,  G06F12/10 ,  G06F12/00

CPC classification number: G06F12/0859 ,  G06F12/0831 ,  G06F12/1045

Abstract: A multiprocessor computer system which maintains cache coherency includes first and second microprocessors each having an associated cache memory storing lines of data. Each line of data has associated protocol bits that indicate a protocol state consistent with write-through, write-back, or write-once cache coherency policies that are selected via a protocol selection terminal for different system configurations. In one configuration, the output and external address terminals of the first microprocessor are coupled to the external and output address terminals, respectively, of the second microprocessor. This configuration enables each microprocessor to snoop memory cycles to main memory initiated by the other microprocessor so that it can be readily determined if a particular cache has the latest version of data.

Abstract translation: 维护高速缓存一致性的多处理器计算机系统包括第一和第二微处理器，每个处理器具有存储数据行的相关联的高速缓存存储器。 每行数据具有相关联的协议位，其指示协议状态与通过用于不同系统配置的协议选择终端选择的直写，回写或一次写入高速缓存一致性策略一致。 在一种配置中，第一微处理器的输出和外部地址端分别耦合到第二微处理器的外部和输出地址端子。 该配置使得每个微处理器能够窥探由另一个微处理器发起的主存储器的存储周期，使得可以容易地确定特定高速缓存是否具有最新版本的数据。

公开(公告)号：USD308179S

公开(公告)日：1990-05-29

申请号：US927424

申请日：1986-11-05

Applicant: David Perlmutter ,  Jay Perlmutter

Designer： David Perlmutter ,  Jay Perlmutter

公开(公告)号：US5265213A

公开(公告)日：1993-11-23

申请号：US625761

申请日：1990-12-10

Applicant: Uri C. Weiser ,  David Perlmutter ,  Yaakov Yaari

Inventor： Uri C. Weiser ,  David Perlmutter ,  Yaakov Yaari

IPC: G06F9/38

CPC classification number: G06F9/3804 ,  G06F9/3844

Abstract: A pipeline instruction processor for executing instructions stored in an instruction memory, including a plurality of branch instructions. The instruction processor includes a branch target buffer which contains target instructions and target addresses corresponding to branch instructions. The target instruction data is indexed according to the address of the instruction which precedes the branch instruction. Also included in the branch target buffer is history data indicating whether the branch was taken. The instruction processor also includes two execution units. The present invention employs logic which allows a branch instruction and its target instruction stored in the branch target buffer to be executed concurrently in the two execution units according to the history data stored in the branch target buffer. Since the branch instructions and their target instructions are executed during the same cycle, branch instructions appear to be executed in zero cycles.

Abstract translation: 一种用于执行存储在指令存储器中的指令的流水线指令处理器，包括多个分支指令。 指令处理器包括分支目标缓冲器，其包含与分支指令对应的目标指令和目标地址。 目标指令数据根据分支指令之前的指令的地址进行索引。 还包括在分支目标缓冲器中的是指示分支是否被采取的历史数据。 指令处理器还包括两个执行单元。 本发明采用根据存储在分支目标缓冲器中的历史数据，允许在两个执行单元中同时执行存储在分支目标缓冲器中的分支指令及其目标指令的逻辑。 由于分支指令及其目标指令在同一周期内执行，所以分支指令似乎以零周期执行。

公开(公告)号：US3936744A

公开(公告)日：1976-02-03

申请号：US465600

申请日：1974-04-30

Applicant: David Perlmutter

Inventor： David Perlmutter

IPC: G01R31/00 ,  G01R31/02 ,  G01R15/12

CPC classification number: G01R31/02 ,  G01R31/006

Abstract: A tester for a solid state voltage regulator includes two parallel branches available for interconnection to the two output contacts of the voltage regulator. The two branches both interconnect to the high voltage side of a battery. One of the branches includes a resistor in parallel combination with an indicator bulb. One of the branches includes a normally open switch. For use with automobile alternators having a built-in regulator, the tester can be connected directly to the regulator and test both the regulator and the alternator. When the regulator is independent of the alternator, it can be tested by itself by using actual rotor current available from an alternator used in conjunction with the tester. The on/off condition of the indicator bulb, when the switch and various contact terminals are interconnected, provides an indication of the effective operation of the regulator. A volt meter can be included integrally with the tester to provide output readings of the regulator.

Abstract translation: 用于固态电压调节器的测试器包括可用于互连到电压调节器的两个输出触点的两个并联支路。 两个分支都互连到电池的高压侧。 一个分支包括与指示灯并联组合的电阻器。 其中一个分支机构包括常开开关。 为了与内置调节器的汽车交流发电机一起使用，测试仪可以直接连接到调节器，同时测试调节器和交流发电机。 当调节器独立于交流发电机时，可以通过使用与测试仪一起使用的交流发电机可用的实际转子电流进行测试。 当开关和各种接触端子相互连接时，指示灯的开/关状态提供了调节器有效运行的指示。 测试仪可以集成一个电压表，以提供稳压器的输出读数。