公开(公告)号：US20130124831A1

公开(公告)日：2013-05-16

申请号：US13730842

申请日：2012-12-29

Applicant: Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benney Eitan

Inventor： Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benney Eitan

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F7/49921 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30192 ,  G06F9/30196

Abstract: An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.

公开(公告)号：US20110252408A1

公开(公告)日：2011-10-13

申请号：US12755440

申请日：2010-04-07

Applicant: Rachel Tzoref ,  Moshe Klausner ,  Roni Kupershtok ,  Yousef Shajrawi ,  Yaakov Yaari

Inventor： Rachel Tzoref ,  Moshe Klausner ,  Roni Kupershtok ,  Yousef Shajrawi ,  Yaakov Yaari

IPC: G06F9/44

CPC classification number: G06F11/3471 ,  G06F11/3409 ,  G06F2201/865

Abstract: Detecting optimization opportunities is enabled by utilizing a trace of a target concurrent computer program and determining a relation between data objects accessed during the tracked execution. The relation may be stored in a Temporal Relation Graph (TRG), in an extended-TRG or another data structure. The relation may be affected by temporally-adjacent accesses to data objects. The relation may further be affected by accesses to data objects performed during critical sections of the target program.

Abstract translation: 通过利用目标并发计算机程序的跟踪并确定在跟踪执行期间访问的数据对象之间的关系，可以实现检测优化机会。 关系可以存储在时间关系图（TRG）中，在扩展TRG或其他数据结构中。 关系可能受时间上相邻的数据对象访问的影响。 该关系可能进一步受到对在目标程序的关键部分期间执行的对数据对象的访问的影响。

公开(公告)号：US20110093682A1

公开(公告)日：2011-04-21

申请号：US12975807

申请日：2010-12-22

Applicant: ALEXANDER PELEG ,  YAAKOV YAARI ,  MILLIND MITTAL ,  LARRY M. MENNEMEIER ,  BENNY EITAN

Inventor： ALEXANDER PELEG ,  YAAKOV YAARI ,  MILLIND MITTAL ,  LARRY M. MENNEMEIER ,  BENNY EITAN

IPC: G06F15/80 ,  G06F9/02

CPC classification number: G06F9/30036 ,  G06F7/49921 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30192 ,  G06F9/30196

Abstract: An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to pack the packed data responsive to a pack instruction received by the decoder. A first packed data element and a second packed data element are received from the first source register. A third packed data element and a fourth packed data element are received from the second source register. The circuit packs packing a portion of each of the packed data elements into a destination register resulting with the portion from second packed data element adjacent to the portion from the first packed data element, and the portion from the fourth packed data element adjacent to the portion from the third packed data element.

Abstract translation: 一种装置包括指令解码器，第一和第二源寄存器和耦合到解码器的电路，用于从源寄存器接收压缩数据，并响应于解码器接收到的包指令对压缩数据进行打包。 从第一源寄存器接收第一打包数据元素和第二打包数据元素。 从第二源寄存器接收第三打包数据元素和第四打包数据元素。 所述电路包装将每个打包数据元素的一部分包装到目的地寄存器中，其结果是来自与来自第一打包数据元素的部分相邻的第二打包数据元素的部分，以及来自与该部分相邻的第四打包数据元素的部分 从第三个打包的数据元素。

公开(公告)号：US07530056B1

公开(公告)日：2009-05-05

申请号：US12060238

申请日：2008-03-31

Applicant: Yaakov Yaari ,  Andre Heilper

Inventor： Yaakov Yaari ,  Andre Heilper

IPC: G06F9/44

CPC classification number: G06F11/3604 ,  G06F11/3644 ,  G06F11/366

Abstract: The invention provides an improved method and method for locating the origin of runtime defect in software programs. A differential debugging technique may be implemented to locate the diversion point where two programs start to behave differently. In one approach, the method generally involves running the two programs and generating respective control flow diagrams via a static code analyzer or the like. Tracer and supervisor modules may be used to replace addresses in registers with symbols and/or position-independent offsets, and to locate where differences in the register states occur.

Abstract translation: 本发明提供了一种用于在软件程序中定位运行时缺陷的来源的改进方法和方法。 可以实现差分调试技术来定位两个程序开始行为不同的转移点。 在一种方法中，该方法通常涉及运行两个程序并通过静态代码分析器等产生相应的控制流程图。 跟踪器和管理器模块可以用于用符号和/或与位置无关的偏移来替换寄存器中的地址，并且定位发生寄存器状态的差异。

公开(公告)号：US07461109B2

公开(公告)日：2008-12-02

申请号：US11758767

申请日：2007-06-06

Applicant: Derrick Chu Lin ,  Punit Minocha ,  Alexander D. Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

Inventor： Derrick Chu Lin ,  Punit Minocha ,  Alexander D. Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

IPC: G06F5/01

CPC classification number: G06F7/762 ,  G06F5/01 ,  G06F7/49994 ,  G06F7/76 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30167 ,  G06F9/3885

Abstract: A method and apparatus for providing, in a processor, a shift operation on a packed data element having multiple values. One embodiment of a central processing unit (CPU) includes instruction fetch logic to fetch a single-instruction-multiple-data (SIMD) shift instruction. A register stores a multiple data elements to be operated upon by the SIMD shift instruction. A barrel shifter concurrently shifts the data elements in a bit-wise manner by a variable number of bit positions in response to the SIMD shift instruction.

Abstract translation: 一种用于在处理器中提供对具有多个值的压缩数据元素进行移位操作的方法和装置。 中央处理单元（CPU）的一个实施例包括提取单指令多数据（SIMD）移位指令的指令提取逻辑。 寄存器存储通过SIMD移位指令来操作的多个数据元素。 桶形移位器响应于SIMD移位指令，同时将数据元素按比特方式移位可变数目的位位置。

公开(公告)号：US07430733B1

公开(公告)日：2008-09-30

申请号：US11940750

申请日：2007-11-15

Applicant: Yaakov Yaari

Inventor： Yaakov Yaari

IPC: G06F9/45

CPC classification number: G06F8/443 ,  G06F8/75

Abstract: A method of validating binary code transformation in one aspect includes analyzing original program and transform program. Control flow graphs are generated for both programs. The two graphs are traversed to create respective linear invariant representations. The linear representations are compared to identify incorrect transformations.

Abstract translation: 一方面验证二进制码变换的方法包括分析原始程序和变换程序。 生成两个程序的控制流程图。 遍历两个图形以创建相应的线性不变量表示。 比较线性表示以识别不正确的变换。

公开(公告)号：US07117232B2

公开(公告)日：2006-10-03

申请号：US11140454

申请日：2005-05-27

Applicant: Derrick Chu Lin ,  Punit Minocha ,  Alexander D. Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

Inventor： Derrick Chu Lin ,  Punit Minocha ,  Alexander D. Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

IPC: G06F5/01

CPC classification number: G06F7/762 ,  G06F5/01 ,  G06F7/49994 ,  G06F7/76 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30167 ,  G06F9/3885

Abstract: A method and apparatus for providing, in a processor, a shift operation on a packed data element having multiple values. The apparatus having multiple muxes, each of the multiple muxes having a first input, a second input, a select input and an output. Each of the multiple bits that represent a shifted packed intermediate result on a first bus is coupled to the corresponding first input. Each of the multiple bits representing a replacement bit for one of the multiple values is coupled to a corresponding second input. Each of the multiple bits driven by a correction circuit is coupled to a corresponding select input. Each output corresponds to a bit of a shifted packed result.

公开(公告)号：US06631389B2

公开(公告)日：2003-10-07

申请号：US09747122

申请日：2000-12-22

Applicant: Derrick Chu Lin ,  Punit Minocha ,  Alexander D. Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

Inventor： Derrick Chu Lin ,  Punit Minocha ,  Alexander D. Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

IPC: G06F501

CPC classification number: G06F7/762 ,  G06F5/01 ,  G06F7/49994 ,  G06F7/76 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30167 ,  G06F9/3885

Abstract: An apparatus for performing a shift operation on a packed data element having a multiple values. The apparatus having multiple muxes, each of the multiple muxes having a first input, a second input, a select input and an output. Each of the multiple bits that represent a shifted packed intermediate result on a first bus is coupled to the corresponding first input. Each of the multiple bits representing a replacement bit for one of the multiple values is coupled to a corresponding second input. Each of the multiple bits driven by a correction circuit is coupled to a corresponding select input. Each output corresponds to a bit of a shifted packed result.

Abstract translation: 一种用于对具有多个值的压缩数据元素执行移位操作的装置。 所述装置具有多个多路复用器，所述多个多路复用器中的每一个具有第一输入，第二输入，选择输入和输出。 表示在第一总线上的移位的打包中间结果的多个比特中的每一个被耦合到对应的第一输入。 表示多个值之一的替换位的多个比特中的每一个被耦合到对应的第二输入。 由校正电路驱动的多个比特中的每一个被耦合到对应的选择输入。 每个输出对应于移位包装结果的一位。

公开(公告)号：US5675526A

公开(公告)日：1997-10-07

申请号：US756708

申请日：1996-11-26

Applicant: Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

Inventor： Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

IPC: G06F9/305 ,  G06F5/00 ,  G06F7/52 ,  G06F9/30 ,  G06F9/302 ,  G06F9/38 ,  G06F7/38

CPC classification number: G06F7/53 ,  G06F9/30014 ,  G06F9/30025 ,  G06F9/30036 ,  G06F9/3885 ,  G06F2207/3828 ,  G06F7/49921

Abstract: A processor. The processor includes a decoder being coupled to receive a control signal. The control signal has a first source address, a second source address, a destination address, and an operation field. The first source address corresponds to a first location. The second source address corresponds to a second location. The destination address corresponds to a third location. The operation field indicates that a type of packed data multiply operation is to be performed. The processor further includes a circuit being coupled to the decoder. The circuit is for multiplying a first packed data being stored at the first location with a second packed data being stored at the second location. The circuit is further for communicating a corresponding result packed data to the third location.

Abstract translation: 处理器 处理器包括被耦合以接收控制信号的解码器。 控制信号具有第一源地址，第二源地址，目的地地址和操作字段。 第一个源地址对应于第一个位置。 第二源地址对应于第二位置。 目的地址对应于第三个位置。 操作字段指示要执行一种打包数据乘法运算。 处理器还包括耦合到解码器的电路。 该电路用于将在第一位置处存储的第一打包数据与存储在第二位置处的第二打包数据相乘。 电路还用于将相应的结果打包数据传送到第三位置。

公开(公告)号：US08850270B2

公开(公告)日：2014-09-30

申请号：US13552665

申请日：2012-07-19

Applicant: Andre Heiper ,  Aharon Kupershtok ,  Yaakov Yaari

Inventor： Andre Heiper ,  Aharon Kupershtok ,  Yaakov Yaari

IPC: G06F11/00

CPC classification number: G06F11/3676

Abstract: Computer-implemented method, computerized apparatus and a computer program product for test selection. The computer-implemented method comprising: obtaining a test suite comprising a plurality of tests for a Software Under Test (SUT); and selecting a subset of the test suite, wherein the subset provides coverage of the SUT that correlates to a coverage by a workload of the SUT, wherein the workload defines a set of input events to the SUT thereby defining portions of the SUT that are to be invoked during execution.

Abstract translation: 计算机实现的方法，计算机化设备和用于测试选择的计算机程序产品。 该计算机实现的方法包括：获得包括用于被测软件（SUT）的多个测试的测试套件; 以及选择所述测试套件的子集，其中所述子集提供与所述SUT的工作负载相关联的所述SUT的覆盖，其中所述工作负载定义到所述SUT的一组输入事件，从而定义所述SUT的部分， 在执行期间被调用。