CMOS circuit for maintaining a constant slew rate
    1.
    发明授权
    CMOS circuit for maintaining a constant slew rate 有权
    CMOS电路,用于保持恒定的转换速率

    公开(公告)号:US06501292B1

    公开(公告)日:2002-12-31

    申请号:US09517783

    申请日:2000-03-02

    申请人: David S. Nack

    发明人: David S. Nack

    IPC分类号: H03K1716

    摘要: A CMOS circuit maintains a constant slew rate over a range of environmental or process conditions. The circuit includes an output stage having a slew rate that is a function of the switching characteristic of the output stage and a bias current. A current adjustment stage adjusts the bias current in view of the switching characteristic to maintain a substantially constant slew rate. The slew rate of the output stage may be tuned to a desired level. A clamp may also be used to limit the voltage variations at the output stage.

    摘要翻译: CMOS电路在一系列环境或工艺条件下保持恒定的压摆率。 电路包括具有作为输出级的开关特性和偏置电流的函数的转换速率的输出级。 考虑到开关特性,电流调节级调节偏置电流以保持大致恒定的转换速率。 输出级的转换速率可以被调谐到期望的水平。 也可以使用钳位来限制输出级的电压变化。

    Single ended controlled current source
    2.
    发明授权
    Single ended controlled current source 失效
    单端控制电流源

    公开(公告)号:US06891428B1

    公开(公告)日:2005-05-10

    申请号:US10722544

    申请日:2003-11-28

    CPC分类号: H03M1/0863 H03M1/747

    摘要: An apparatus and method for a controlled current source are provided. The apparatus may include at least one current cell. Each current cell includes first, second and third transistors. The first transistor can be configured as a switch transistor. The second transistor can be configured as a current controller and can be coupled in series with the first transistor. The third transistor has a gate and a substrate coupled to a gate and a substrate of the second transistor, respectively. The drain and source of the third transistor can be coupled to a second input configured to receive a second signal that is a compliment of a first signal received at an input of the first transistor.

    摘要翻译: 提供了一种用于受控电流源的装置和方法。 该装置可以包括至少一个当前小区。 每个当前单元包括第一,第二和第三晶体管。 第一晶体管可以配置为开关晶体管。 第二晶体管可以被配置为电流控制器并且可以与第一晶体管串联耦合。 第三晶体管分别具有与第二晶体管的栅极和衬底耦合的栅极和衬底。 第三晶体管的漏极和源极可以耦合到第二输入端,其被配置为接收第二信号,该第二信号是在第一晶体管的输入处接收到的第一信号的补充。

    Modified third order phase-locked loop
    3.
    发明授权
    Modified third order phase-locked loop 失效
    修改三阶锁相环

    公开(公告)号:US06188739B1

    公开(公告)日:2001-02-13

    申请号:US08954914

    申请日:1997-10-21

    IPC分类号: H03D324

    摘要: A phase-locked loop circuit is disclosed which exhibits a wide capture range and a low quality factor (Q) to prevent ringing and improve stability without adding area, increasing power consumption or increasing noise levels. The phase-locked loop includes a comparator to generate an error signal, an oscillator which generates an output signal in response to a control signal and a loop filter which generates the control signal based on the error signal. The loop filter includes a first integrator operatively coupled through a threshold limit detector to a second integrator. The threshold limit detector supplies an electric charge to the second integrator only when the first integrator is proximate to either an upper limit or a lower limit of the first integrator's operating range. The oscillator generates the output signal which tracks the input reference signal frequency as an integer multiple of the input reference signal frequency. The oscillator generates the output signal in response to varying current levels of the control signal. The loop filter further includes a pump-up and a pump-down charge pump that act in tandem under activation by the threshold limit detector. The loop filter includes a duty cycle limiter switch that limits the supply of the charge to the second integrator to a predetermined time period.

    摘要翻译: 公开了一种锁相环电路,其具有宽的捕获范围和低品质因数(Q),以防止振铃并且在不增加面积,增加功率消耗或增加噪声水平的情况下提高稳定性。 锁相环包括用于产生误差信号的比较器,响应于控制信号产生输出信号的振荡器和基于误差信号产生控制信号的环路滤波器。 环路滤波器包括通过阈值极限检测器可操作地耦合到第二积分器的第一积分器。 仅当第一积分器接近第一积分器的操作范围的上限或下限时,阈值检测器仅向第二积分器提供电荷。 振荡器产生跟踪输入参考信号频率作为输入参考信号频率的整数倍的输出信号。 振荡器响应于控制信号的变化的电流电平而产生输出信号。 环路滤波器还包括泵送和泵浦电荷泵,其在由阈值限制检测器激活的情况下串联起作用。 环路滤波器包括占空比限制器开关,其将向第二积分器的电荷供应限制到预定时间段。