公开(公告)号：US07287185B2

公开(公告)日：2007-10-23

申请号：US10819241

申请日：2004-04-06

Applicant: Kevin David Safford ,  Donald Charles Soltis, Jr.

Inventor： Kevin David Safford ,  Donald Charles Soltis, Jr.

IPC: G06F11/00

CPC classification number: G06F9/30181 ,  G06F9/30076 ,  G06F9/30189 ,  G06F9/3851 ,  G06F11/1629 ,  G06F2201/845

Abstract: In one aspect of the present invention, a circuit is provided which implements an instruction set architecture defining a first instruction group, a second instruction group to enter a high-reliability mode of operation, and a third instruction group to enter a non-high-reliability mode of operation. The circuit includes means for causing the circuit to enter the high-reliability mode of operation in response to receiving the second instruction group; means for causing the circuit to enter the non-high-reliability mode of operation in response to receiving the third instruction group; first execution means for executing the first instruction group in the high-reliability mode of operation if the circuit is in the high-reliability mode of operation; and second execution means for executing the first instruction group in the non-high-reliability mode of operation if the circuit is in the non-high-reliability mode of operation.

Abstract translation: 在本发明的一个方面，提供一种电路，其实现定义第一指令组的指令集架构，进入高可靠性操作模式的第二指令组，以及进入非高速模式的第三指令组， 可靠的运行模式。 电路包括用于响应于接收到第二指令组而使电路进入高可靠性操作模式的装置; 响应于接收到第三指令组使电路进入非高可靠性操作模式的装置; 如果电路处于高可靠性操作模式，则在高可靠性操作模式下执行第一指令组的第一执行装置; 以及第二执行装置，用于如果电路处于非高可靠性操作模式，则以非高可靠性操作模式执行第一指令组。

公开(公告)号：US07237144B2

公开(公告)日：2007-06-26

申请号：US10818994

申请日：2004-04-06

Applicant: Kevin David Safford ,  Donald Charles Soltis, Jr. ,  Eric Richard Delano

Inventor： Kevin David Safford ,  Donald Charles Soltis, Jr. ,  Eric Richard Delano

IPC: G06F11/00

CPC classification number: G06F11/1641 ,  G06F11/1625 ,  G06F2201/845

Abstract: A system is provided which includes a microprocessor comprising a first processing unit to generate a first output signal and a second processing unit to generate a second output signal, and comparison means, coupled to the microprocessor, to detect whether the first output signal differs from the second output signal.

Abstract translation: 提供了一种系统，其包括微处理器，该微处理器包括产生第一输出信号的第一处理单元和用于产生第二输出信号的第二处理单元，以及耦合到微处理器的比较装置，以检测第一输出信号是否与 第二输出信号。

公开(公告)号：US07139936B2

公开(公告)日：2006-11-21

申请号：US10645567

申请日：2003-08-22

Applicant: Jeremy Petsinger ,  Kevin David Safford ,  Karl P. Brummel ,  Russell C. Brockmann ,  Bruce A. Long ,  Patrick Knebel

Inventor： Jeremy Petsinger ,  Kevin David Safford ,  Karl P. Brummel ,  Russell C. Brockmann ,  Bruce A. Long ,  Patrick Knebel

IPC: G06F11/00

CPC classification number: G06F11/261

Abstract: An apparatus verifies the correctness of a behavioral model of a microcode machine, where the microcode machine is operable in a native state and an emulated state. The apparatus includes means for producing the native state, means for producing the emulated state, and means for comparing the native state and the emulated state. Corresponding to the apparatus, a method verifies the correctness of a processor behavioral model, where the processor operates in a native mode state and an emulated mode state. The method includes determining if a macroinstruction to be executed is a native instruction, and, if the macroinstruction is a native instruction, executing the native instruction, the execution producing the native mode state of the processor. The method further includes, if the macroinstruction is not a native instruction, fetching the macroinstruction, providing microinstructions corresponding to the macroinstruction, and executing the microinstructions, the execution producing the native mode state of the processor. Finally, the method includes executing the macroinstruction, the execution producing an emulated state of the processor, and comparing the native mode state the of the processor with the emulated state of the processor.

Abstract translation: 一种装置验证微代码机器的行为模型的正确性，其中微代码机器可操作于原始状态和仿真状态。 该装置包括用于产生天然状态的装置，用于产生仿真状态的装置，以及用于比较天然状态和仿真状态的装置。 对应于该装置，一种方法验证处理器行为模型的正确性，其中处理器以本机模式状态和仿真模式状态操作。 该方法包括确定要执行的宏指令是否是本地指令，以及如果宏指令是本机指令，则执行本机指令，则产生处理器的本机模式状态的执行。 该方法还包括：如果宏指令不是本机指令，则获取宏指令，提供与宏指令相对应的微指令，以及执行微指令，执行产生处理器的本机模式状态。 最后，该方法包括执行宏指令，执行产生处理器的仿真状态，以及将处理器的本机模式状态与处理器的仿真状态进行比较。

公开(公告)号：US07085959B2

公开(公告)日：2006-08-01

申请号：US10187833

申请日：2002-07-03

Applicant: Kevin David Safford

Inventor： Kevin David Safford

IPC: G06F11/00

CPC classification number: G06F11/2038 ,  G06F11/1641 ,  G06F11/165 ,  G06F11/1658 ,  G06F11/2025 ,  G06F2201/845

Abstract: An apparatus, operating on an advanced multi-core processor architecture, and a corresponding method, are used to enhance recovery from loss of lock step in a multi-processor computer system. The apparatus for recovery from loss of lock step includes multiple processor units operating in the computer system, each of the processor units having at least two processor units operating in lock step, and at least one idle processor unit operating in lock step; and a controller coupled to the two processor units operating in lock step and the idle processor unit. The controller includes mechanisms for copying an architected state of each of the two lock step processor units to the idle processor unit.

Abstract translation: 在多处理器计算机系统中，使用以先进的多核处理器架构运行的装置和相应的方法来增强从锁定步骤的丢失中的恢复。 用于从失锁步骤恢复的装置包括在计算机系统中操作的多个处理器单元，每个处理器单元具有以锁定步骤操作的至少两个处理器单元，以及以锁定步骤操作的至少一个空闲处理器单元; 以及耦合到处于锁定步骤的两个处理器单元和空闲处理器单元的控制器。 控制器包括用于将两个锁步骤处理器单元中的每一个的架构状态复制到空闲处理器单元的机构。

公开(公告)号：US06668315B1

公开(公告)日：2003-12-23

申请号：US09449804

申请日：1999-11-26

Applicant: Kevin David Safford ,  Patrick Knebel

Inventor： Kevin David Safford ,  Patrick Knebel

IPC: G06F9455

CPC classification number: G06F9/3861 ,  G06F9/30032 ,  G06F9/30174 ,  G06F9/3885

Abstract: A processor based computer system having dependency checking logic and a register stack, wherein the system overrides the dependency logic such that move instructions associated with the stack registers may be executed in parallel. The system operates such that it can be determined whether a stack underflow exception has occurred and if it has, the move instructions can be flushed, and a micro-code handler algorithm invoked that operates to allow execution of the move instructions in parallel without a stack underflow exception.

Abstract translation: 具有依赖性检查逻辑和寄存器堆栈的基于处理器的计算机系统，其中所述系统覆盖所述依赖性逻辑，使得可以并行执行与所述堆栈寄存器相关联的移动指令。 系统操作使得可以确定是否发生堆栈下溢异常，并且如果已经发生了移动指令，则可以刷新移动指令，并且调用微代码处理器算法来操作以允许平行地执行移动指令而没有堆栈 下溢异常。

公开(公告)号：US06643800B1

公开(公告)日：2003-11-04

申请号：US09496367

申请日：2000-02-02

Applicant: Kevin David Safford ,  Patrick Knebel ,  Russell C Brockmann ,  Karl P Brummel ,  M A Susith Rohana Fernando

Inventor： Kevin David Safford ,  Patrick Knebel ,  Russell C Brockmann ,  Karl P Brummel ,  M A Susith Rohana Fernando

IPC: G06F1100

CPC classification number: G06F9/30174

Abstract: An apparatus and a method of testing computer microarchitectures has a test writer create a test sequence written directly in microinstructions (both native-mode and emulation-only microinstructions). The microinstruction sequence is then inserted into a reprogrammable microcode storage, replacing the normal sequence of microinstructions for a given macroinstruction. In order to execute the microinstructions, the test writer can issue the macroinstruction. The method may be implemented in a simulation model where one set of microinstructions in the reprogrammable microcode storage can be easily replaced. The method may also be applied to an actual microprocessor implementation.

Abstract translation: 一种测试计算机微体系结构的设备和方法，测试笔者创建一个直接写入微指令（包括天体模式和仅仿真微指令）的测试序列。 然后将微指令序列插入可重编程的微代码存储器中，替换给定宏指令的微指令的正常序列。 为了执行微指令，测试者可以发出宏指令。 该方法可以在仿真模型中实现，其中可重新编程的微代码存储器中的一组微指令可以容易地替换。 该方法也可以应用于实际的微处理器实现。

公开(公告)号：US07370232B2

公开(公告)日：2008-05-06

申请号：US11454087

申请日：2006-06-16

Applicant: Kevin David Safford

Inventor： Kevin David Safford

IPC: G06F11/00

CPC classification number: G06F11/2038 ,  G06F11/1641 ,  G06F11/165 ,  G06F11/1658 ,  G06F11/2025 ,  G06F2201/845

Abstract: An apparatus, operating on an advanced multi-core processor architecture, and a corresponding method, are used to enhance recovery from loss of lock step in a multi-processor computer system. The apparatus for recovery from loss of lock step includes multiple processor units operating in the computer system, each of the processor units having at least two processor units operating in lock step, and at least one idle processor unit operating in lock step; and a controller coupled to the two processor units operating in lock step and the idle processor unit. The controller includes mechanisms for copying an architected state of each of the two lock step processor units to the idle processor unit.

Abstract translation: 在多处理器计算机系统中，使用以先进的多核处理器架构运行的装置和相应的方法来增强从锁定步骤的丢失中的恢复。 用于从失锁步骤恢复的装置包括在计算机系统中操作的多个处理器单元，每个处理器单元具有以锁定步骤操作的至少两个处理器单元，以及以锁定步骤操作的至少一个空闲处理器单元; 以及耦合到处于锁定步骤的两个处理器单元和空闲处理器单元的控制器。 控制器包括用于将两个锁步骤处理器单元中的每一个的架构状态复制到空闲处理器单元的机构。

公开(公告)号：US07343479B2

公开(公告)日：2008-03-11

申请号：US10602916

申请日：2003-06-25

Applicant: Patrick Knebel ,  Kevin David Safford ,  Donald Charles Soltis, Jr. ,  Joel D Lamb ,  Stephen R. Undy ,  Russell C Brockmann

Inventor： Patrick Knebel ,  Kevin David Safford ,  Donald Charles Soltis, Jr. ,  Joel D Lamb ,  Stephen R. Undy ,  Russell C Brockmann

IPC: G06F9/455

CPC classification number: G06F9/30174 ,  G06F9/30167 ,  G06F9/382 ,  G06F9/3853

Abstract: The present invention is a method for implementing two architectures on a single chip. The method uses a fetch engine to retrieve instructions. If the instructions are macroinstructions, then it decodes the macroinstructions into microinstructions, and then bundles those microinstructions using a bundler, within an emulation engine. The bundles are issued in parallel and dispatched to the execution engine and contain pre-decode bits so that the execution engine treats them as microinstructions. Before being transferred to the execution engine, the instructions may be held in a buffer. The method also selects between bundled microinstructions from the emulation engine and native microinstructions coming directly from the fetch engine, by using a multiplexer or other means. Both native microinstructions and bundled microinstructions may be held in the buffer. The method also sends additional information to the execution engine.

Abstract translation: 本发明是用于在单个芯片上实现两个架构的方法。 该方法使用提取引擎来检索指令。 如果指令是宏指令，则将宏指令解码为微指令，然后在仿真引擎内使用捆绑器捆绑这些微指令。 捆绑包并行发布并分发到执行引擎并包含预解码位，以便执行引擎将它们视为微指令。 在被传送到执行引擎之前，可以将指令保存在缓冲器中。 该方法还可以通过使用多路复用器或其他方式，从模拟引擎的捆绑微指令和直接从获取引擎进行的本机微指令之间进行选择。 本地微指令和捆绑的微指令都可以保存在缓冲区中。 该方法还向执行引擎发送附加信息。

公开(公告)号：US07155721B2

公开(公告)日：2006-12-26

申请号：US10183563

申请日：2002-06-28

Applicant: Kevin David Safford ,  Jeremy P. Petsinger

Inventor： Kevin David Safford ,  Jeremy P. Petsinger

IPC: G06F9/46 ,  G06F15/00 ,  G06F11/00

CPC classification number: G06F11/1683 ,  G06F9/30189 ,  G06F9/3824 ,  G06F9/3828 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/3887 ,  G06F11/1641

Abstract: An apparatus for communicating between lock step is incorporated on two or more processors operating in a lock step mode. Each of the processors includes processor logic to execute a code sequence, and an identical code sequence is executed by the processor logic. The apparatus further includes a processor-specific resource referenced by the code sequence. A multiplexer is coupled to the processor-specific resource, and is controlled to read data based on the identification. Coupled to the processors is a lock step logic block operable to read and compare the output of each of the processors. The lock step logic determines if operation of the processors is in a lock step mode or in an independent processor mode. Such determination may be made by the lock step logic turning off, for example.

Abstract translation: 用于锁定步骤之间的通信的装置被结合在以锁定步骤模式操作的两个或多个处理器上。 每个处理器包括执行代码序列的处理器逻辑，并且处理器逻辑执行相同的代码序列。 该装置还包括由代码序列引用的特定于处理器的资源。 多路复用器耦合到特定于处理器的资源，并被控制以基于识别来读取数据。 耦合到处理器的是锁步骤逻辑块，可操作以读取和比较每个处理器的输出。 锁定步骤逻辑确定处理器的操作是处于锁定步骤模式还是处于独立处理器模式。 例如，可以通过锁定步骤逻辑关闭来进行这种确定。

公开(公告)号：US06820190B1

公开(公告)日：2004-11-16

申请号：US09496844

申请日：2000-02-02

Applicant: Patrick Knebel ,  Kevin David Safford

Inventor： Patrick Knebel ,  Kevin David Safford

IPC: G06F930

CPC classification number: G06F9/30174 ,  G06F9/30036 ,  G06F9/30101 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30116 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3857 ,  G06F9/3865

Abstract: The present invention is a method for processing instructions by decomposing a macroinstruction into at least two microinstructions, executing the microinstructions in parallel, and linking the microinstructions such that they appear as though they were executed as a single functional unit. The present invention operates by determining whether certain exceptions occur in either of the functional units, according to SSE rules for exceptions. If an exception does occur in any of the linked microinstructions, then the execution of each of those microinstructions is canceled. This avoids the necessity of a back-off or undo mechanism.

Abstract translation: 本发明是一种通过将宏指令分解成至少两个微指令来并行执行微指令来处理指令的方法，并且连接微指令，使得它们看起来像单个功能单元一样被执行。 根据例外的SSE规则，本发明通过确定在任一功能单元中是否发生某些异常来进行操作。 如果在任何连接的微指令中发生异常，那么这些微指令中的每一个的执行将被取消。 这避免了退出或撤销机制的必要性。