公开(公告)号：US12119837B2

公开(公告)日：2024-10-15

申请号：US17607259

申请日：2020-04-30

Applicant: SAFRAN AIRCRAFT ENGINES

Inventor： Christophe Pierre Georges Martin

IPC: H03M1/10 ,  G06F11/16

CPC classification number: H03M1/1076 ,  G06F11/165

Abstract: Methods are provided for supervising a motor control unit with at least two separate channels, each of the two channels including at least: means for executing a given application task AS, the application task AS including a plurality of successively executed computations between which latency periods elapse; a first component capable of performing the computations; a second component capable of storing data; the application tasks AS of the channels being capable of communicating. The method includes the following steps: a) detecting a latency period; b) performing, during this latency period, an operating state test of at least one of the components; and c) determining a state of the component corresponding to a failure state or a healthy state.

公开(公告)号：US11915022B2

公开(公告)日：2024-02-27

申请号：US15098910

申请日：2016-04-14

Applicant: Red Hat, Inc.

Inventor： David A. Gilbert

IPC: G06F9/455 ,  G06F11/16 ,  G06F11/20

CPC classification number: G06F9/45558 ,  G06F11/165 ,  G06F11/1637 ,  G06F11/1666 ,  G06F11/1675 ,  G06F11/2035 ,  G06F11/2048 ,  G06F11/2082 ,  G06F2009/45583 ,  G06F2201/815

Abstract: Mechanisms for reducing memory inconsistencies between two synchronized computing devices are provided. A first hypervisor module of a first computing device iteratively determines that content of a memory page of a plurality of memory pages has been modified. The content of the memory page is sent to a second hypervisor module on a second computing device. At least one other memory page of the plurality of memory pages is identified, and a verification value based on the content of the at least one other memory page is generated. The verification value and a memory page identifier that identifies the at least one other memory page is sent to the second hypervisor module on the second computing device.

公开(公告)号：US11740982B2

公开(公告)日：2023-08-29

申请号：US17826428

申请日：2022-05-27

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Cheng Zhang

IPC: G06F11/00 ,  G06F11/20 ,  H04L1/22 ,  H04L67/1097 ,  G06F11/16

CPC classification number: G06F11/2033 ,  G06F11/165 ,  G06F11/1645 ,  G06F11/2025 ,  G06F11/2035 ,  G06F11/2048 ,  G06F11/2097 ,  H04L1/22 ,  H04L67/1097 ,  G06F11/2028 ,  G06F11/2056 ,  G06F2201/805

Abstract: The present disclosure describes example service takeover methods, storage devices, and service takeover apparatuses. In one example method, when a communication fault occurs between two storage devices in a storage system, the two storage devices respectively obtain running statuses of the two storage devices. A running status can reflect current usage of one or more system resources of a particular storage device. Then, a delay duration is determined according to the running statuses, where the delay duration is a duration for which the storage device waits before sending an arbitration request to a quorum server. The two storage devices respectively send, after the delay duration, arbitration requests to the quorum server to request to take over a service. The quorum server then can select a storage device in a relatively better running status to take over a host service.

公开(公告)号：US20190042376A1

公开(公告)日：2019-02-07

申请号：US15669493

申请日：2017-08-04

Applicant: The Boeing Company

Inventor： Alexander Shyon Babazadeh

IPC: G06F11/18 ,  G06F11/16

CPC classification number: G06F11/184 ,  G06F11/076 ,  G06F11/1641 ,  G06F11/165 ,  G06F11/1658 ,  G06F11/1675 ,  G06F11/181 ,  G06F2201/81 ,  G06F2201/88

Abstract: A transmitting computer for a vehicle is disclosed, and includes a command circuit, a monitor circuit, and a master circuit. The command circuit receives a real-time signal and executes a first set of instructions to analyze the real-time signal, and generates a plurality of command signals based on executing the first set of instructions. The monitor circuit receives the command signals and the real-time signal. The monitor circuit executes a second set of instructions to analyze the real-time signal and generates a plurality of replica signals based on executing the second set of instructions. The monitor circuit generates an initial reset command in response to determining an initial miscompare between one of the plurality of command signals and the plurality of replica signals. The master circuit is in communication with both the command circuit and the monitor circuit and receives an indication that the initial reset command is generated.

公开(公告)号：US20180307574A1

公开(公告)日：2018-10-25

申请号：US15492757

申请日：2017-04-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Tariq Hanif ,  Tin H. To

IPC: G06F11/273 ,  G06F11/22

CPC classification number: G06F11/3688 ,  G06F11/1497 ,  G06F11/1629 ,  G06F11/1641 ,  G06F11/165 ,  G06F11/183 ,  G06F11/187 ,  G06F11/2221 ,  G06F11/2294 ,  G06F11/3457 ,  G06F11/3684 ,  G06F11/3692

Abstract: Embodiments for automated testing of a virtualization management system are described. An example computer-implemented method for automated testing of a virtualization management system includes sending, by a test server, a test case to a plurality of instances of the system under test, the test case sent to each instance of the system under test via each interface from a plurality of interfaces supported by the system under test. The method further includes, for each instance of the system under test, performing multi-interface comparison. The comparison includes comparing, by the test server, responses to the test case from each of the interfaces. The method also includes in response to the responses from each of the interfaces being identical, storing the responses in an instance-response file corresponding to the instance. The method also includes reporting, by the test server, an error in response to the responses from each interface not being identical.

公开(公告)号：US20180074920A1

公开(公告)日：2018-03-15

申请号：US15433206

申请日：2017-02-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jon Hawkes ,  Neil G.S. Young

IPC: G06F11/16 ,  H04L29/06 ,  G06F11/20

CPC classification number: G06F11/1633 ,  G06F11/165 ,  G06F11/2023 ,  G06F11/2028 ,  G06F11/203 ,  G06F11/2035 ,  G06F11/2048 ,  G06F2201/805 ,  G06F2201/81 ,  G06F2201/835 ,  G06F2201/85 ,  G06F2201/875 ,  H04L63/0281

Abstract: Computer-implemented methods and systems are provided for detecting a failed server. The computer-implemented method includes detecting a plurality of servers within a network, allowing each of the plurality of servers to monitor a state of other servers of the plurality of servers, and in response to detecting a failed server, allowing another server of the plurality of servers to complete remaining work of the failed server.

公开(公告)号：US09811429B2

公开(公告)日：2017-11-07

申请号：US14705127

申请日：2015-05-06

Applicant: Renesas Electronics Corporation

Inventor： Nobuyasu Kanekawa ,  Hitoshi Arimitsu ,  Takashi Yasumasu ,  Hideki Matsuyama

IPC: G06F11/16 ,  G06F11/20 ,  G06F11/18

CPC classification number: G06F11/2053 ,  G06F11/1616 ,  G06F11/1641 ,  G06F11/165 ,  G06F11/183 ,  G06F11/187 ,  G06F2201/85

Abstract: The present invention provides a microcontroller which can continue operation even at the time of a failure without making a memory redundant to suppress increase in chip area. The microcontroller includes three or more processors executing the same process in parallel and a storage device. The storage device includes a memory mat having a storage region which is not redundant, an address selection part, a data output part, and a failure recovery part. The address selection part selects a storage region in the memory mat on the basis of three or more addresses issued at the time of an access by the processors. The data output part reads data from the storage region in the memory mat selected by the address selection part. The failure recovery part corrects or masks a failure of predetermined number or less which occurs in the memory mat, the address selection part, and the data output part.

公开(公告)号：US09734023B2

公开(公告)日：2017-08-15

申请号：US14801825

申请日：2015-07-17

Applicant: Renesas Electronics Corporation

Inventor： Osamu Nishii ,  Kiwamu Takada

IPC: G06F11/00 ,  G06F11/16 ,  G06F11/14

CPC classification number: G06F11/1637 ,  G06F11/1004 ,  G06F11/1405 ,  G06F11/1645 ,  G06F11/165 ,  G06F11/1695

Abstract: Conventional semiconductor devices are problematic in that an operation cannot be continued in the event of a failure of one of CPU cores performing a lock step operation and, as a result, reliability cannot be improved. The semiconductor device according to the present invention includes a computing unit including a first CPU core and a second CPU core that perform a lock step operation, wherein the first CPU core and the second CPU core respectively diagnose failures of internal logic circuits, and a sequence control circuit switches the CPU core that outputs data to a shared resource, in the computing unit based on the diagnose result.

公开(公告)号：US09665447B2

公开(公告)日：2017-05-30

申请号：US14140686

申请日：2013-12-26

Applicant: Artesyn Embedded Computing, Inc.

Inventor： Martin Peter John Cornes ,  Pasi Jukka Petteri Vaananen ,  Liu Jiang

IPC: G06F11/00 ,  G06F11/16

CPC classification number: G06F11/1637 ,  G06F11/165

Abstract: A system includes a safety relevant component that generates a data packet in response to receiving a request to perform a task and that communicates the data packet. The system further includes a first fail-safe chassis (FSC) that continuously generates a first chassis health signal, that determines whether the data packet is valid, and that selectively determines whether to de-assert the first chassis health signal based on the determination. The system also includes a second FSC that continuously generates a second chassis health signal, that determines whether a copy of the data packet is valid, and that selectively determines whether to de-assert the second chassis health signal based on the determination. The system further includes a safety relay box module that determines whether to instruct the first FSC to operate in a predetermined mode based on the first chassis health signal and the second chassis health signal.

公开(公告)号：US09513903B2

公开(公告)日：2016-12-06

申请号：US14054643

申请日：2013-10-15

Applicant: Industrial Technology Research Institute

Inventor： Yung-Chang Chang ,  Hsing-Chuang Liu ,  Chih-Jen Yang

IPC: G06F11/16 ,  G06F9/30 ,  G06F11/18 ,  H03K19/003 ,  G06F11/14

CPC classification number: G06F9/3001 ,  G06F11/1497 ,  G06F11/1608 ,  G06F11/1629 ,  G06F11/1641 ,  G06F11/165 ,  G06F11/183 ,  G06F11/188 ,  H03K19/0033

Abstract: A fault-tolerant system including a calculation unit and an output synthesizer is provided. The calculation unit receives a first environmental parameter and input data, wherein the calculation unit further includes a first and a second calculation circuits. The first calculation circuit is arranged to perform a calculation on the input data in response to the first environmental parameter to generate a first calculation result. The second calculation circuit is different from the first calculation circuit, and arranged to perform the calculation on the input data in response to the first environmental parameter to generate a second calculation result. The output synthesizer selects a first and a second set of bits from the first and the second calculation result according to a control signal, and synthesizes the first set of bits and the second set of bits in sequence to generate an adjusted calculation result.

Abstract translation: 提供了包括计算单元和输出合成器的容错系统。 计算单元接收第一环境参数和输入数据，其中所述计算单元还包括第一和第二计算电路。 第一计算电路被配置为响应于第一环境参数对输入数据进行计算以产生第一计算结果。 第二计算电路与第一计算电路不同，并且被配置为响应于第一环境参数对输入数据进行计算以产生第二计算结果。 输出合成器根据控制信号从第一和第二计算结果中选择第一组和第二组，并且顺序地合成第一组位和第二组位，以产生经调整的计算结果。