公开(公告)号：US06255904B1

公开(公告)日：2001-07-03

申请号：US09461163

申请日：1999-12-14

Applicant: Giovanni Capodivacca ,  Davide Brambilla

Inventor： Giovanni Capodivacca ,  Davide Brambilla

IPC: H03F114

CPC classification number: H03F1/305

Abstract: The anti-pop circuit includes a unity gain buffer with an input coupled to the source of the reference voltage and an output coupled to the input of the amplifier to accelerate the charging of the input coupling capacitor of the amplifier at every turn-on. The capacitor-charging buffer is automatically disabled before the turning-on of the amplifier. The charging buffer may be enabled at start up by generating an impulse of a pre-established duration at the turn-on instant by a monostable circuit or by disabling it upon verifying the decaying to zero of the charging of current of the input coupling capacitor. The circuit eliminates the popping noise at the turn-on without an excessive delay of the turning-on of the amplifier.

Abstract translation: 反跳线电路包括具有耦合到参考电压源的输入的单位增益缓冲器和耦合到放大器的输入的输出，以在每次导通时加速放大器的输入耦合电容器的充电。 电容充电缓冲器在放大器导通之前自动禁用。 充电缓冲器可以在启动时通过在单通电路的导通瞬间产生预先建立的持续时间的脉冲，或者通过在验证输入耦合电容器的电流的衰减为零时禁用该充电缓冲器。 该电路消除了导通时的爆音噪声，而放大器的导通不会过度延迟。

公开(公告)号：US5942783A

公开(公告)日：1999-08-24

申请号：US594805

申请日：1996-01-31

Applicant: Davide Brambilla ,  Edoardo Botti ,  Paolo Ferrari

Inventor： Davide Brambilla ,  Edoardo Botti ,  Paolo Ferrari

IPC: H01L21/8222 ,  H01L27/06 ,  H01L29/861 ,  H01L29/72

CPC classification number: H01L27/0664

Abstract: A semiconductor circuit includes a semiconductor layer having a surface and a monolithic output stage formed in the semiconductor layer. The monolithic output stage extends to the surface of the semiconductor layer and has a periphery within the semiconductor layer, an output terminal, and a supply terminal. A barrier well is formed in the semiconductor layer and adjacent to at least a portion of the periphery of the monolithic output stage. The barrier well extends to the surface of the semiconductor layer and has a first conductivity. A diode having first and second diode regions is disposed in the semiconductor layer. The first diode region is coupled to the supply terminal. The diode is operable to prevent current flow from the barrier well to the supply terminal when the voltage between the supply and output terminals has a first polarity.

Abstract translation: 半导体电路包括具有形成在半导体层中的表面和单片输出级的半导体层。 单片输出级延伸到半导体层的表面，并且在半导体层内具有周边，输出端和供电端。 屏障阱形成在半导体层中并与单片输出级的周边的至少一部分相邻。 势阱阱延伸到半导体层的表面并且具有第一导电性。 具有第一和第二二极管区的二极管设置在半导体层中。 第一二极管区域耦合到供电端子。 当供电和输出端子之间的电压具有第一极性时，二极管可操作以防止电流从阻挡阱流向电源端子。

公开(公告)号：US20050174705A1

公开(公告)日：2005-08-11

申请号：US11056407

申请日：2005-02-11

Applicant: Davide Brambilla ,  Daniela Nebuloni

Inventor： Davide Brambilla ,  Daniela Nebuloni

IPC: G05F1/56 ,  H02H7/00

CPC classification number: G05F1/56

Abstract: In a device that includes a pair of closed-loop voltage regulators each including an input transconductance stage receiving a reference voltage and a feedback voltage, an intermediate transresistance stage, an output buffer operatively in cascade for generating on an output node the regulated output voltage and negative feedback means for providing the feedback voltage to the input stage, the method includes a circuit that limits the difference between two output regulated voltages. The limiting circuit includes a differential transconductance amplifier input with voltages proportional to the output voltages of the regulators or obtained by adding an offset voltage to the output voltage of the regulators for injecting in, or draining from, an input node of the intermediate stage of one of the regulators, a current as a function of the relative unbalance of the differential transconductance amplifier.

Abstract translation: 在包括一对闭合电压调节器的装置中，每一个包括接收参考电压和反馈电压的输入跨导级，中间跨阻级，可级联的输出缓冲器，用于在输出节点上产生调节的输出电压，以及 负反馈装置用于向输入级提供反馈电压，该方法包括限制两个输出调节电压之间的差的电路。 限制电路包括差分跨导放大器输入，其具有与调节器的输出电压成比例的电压，或者通过将偏移电压加到调节器的输出电压上，以将其输入或从其中间级的输入节点排出 的调节器，作为差分跨导放大器的相对不平衡的函数的电流。

公开(公告)号：US5874852A

公开(公告)日：1999-02-23

申请号：US706068

申请日：1996-08-30

Applicant: Davide Brambilla ,  Daniela Nebuloni ,  Giorgio Rossi ,  Sergio Lecce

Inventor： Davide Brambilla ,  Daniela Nebuloni ,  Giorgio Rossi ,  Sergio Lecce

IPC: G05F3/26 ,  H03F3/345 ,  H03F3/343

CPC classification number: H03F3/345 ,  G05F3/267

Abstract: A current generator circuit with controllable frequency response has at least one current mirror formed of MOS transistors, being powered through a terminal held at a constant voltage, having an input leg through which a reference current (I1) is driven by a first current generator (G1), and having an output leg for generating, on an output terminal (OUT) of the mirror, a mirrored current (I.sub.out) which is proportional to the reference current (I1). The input leg includes at least a first transistor (M1) which is diode-connected and has a control terminal (Ga1) coupled to a corresponding terminal (Ga2) of a second transistor (M2) included in the output leg by an impedance matching circuit configured to hold the same voltage value at both terminals (Ga1 and Ga2). The impedance matching circuit has an adjustable output impedance, specifically lower in value than the value to be had without this circuit. It functions to regulate the impedance on the control node (Ga2) of the second transistor (M2). The invention is equally applicable to N-channel and P-channel MOS transistors. Advantageously, the reference current can be varied by an external signal which is a function of the output signal, to provide feedback regulating features.

Abstract translation: 具有可控频率响应的电流发生器电路具有由MOS晶体管形成的至少一个电流镜，其通过保持在恒定电压的端子供电，具有输入支路，参考电流（I1）由第一电流发生器 G1），并且具有用于在镜的输出端（OUT）上产生与参考电流（I1）成比例的镜像电流（Iout）的输出支路。 输入支路至少包括二极管连接的第一晶体管（M1），并且具有通过阻抗匹配电路耦合到包括在输出支路中的第二晶体管（M2）的对应端子（Ga2）的控制端子（Ga1） 被配置为在两个端子（Ga1和Ga2）处保持相同的电压值。 阻抗匹配电路具有可调节的输出阻抗，具体值低于没有该电路的值。 它用于调节第二晶体管（M2）的控制节点（Ga2）上的阻抗。 本发明同样适用于N沟道和P沟道MOS晶体管。 有利地，参考电流可以通过作为输出信号的函数的外部信号来改变，以提供反馈调节特征。

公开(公告)号：US5210481A

公开(公告)日：1993-05-11

申请号：US808484

申请日：1991-12-17

Applicant: Davide Brambilla ,  Edoardo Botti

Inventor： Davide Brambilla ,  Edoardo Botti

IPC: G05F1/56 ,  H03K17/041 ,  H03K17/082

CPC classification number: H03K17/04113 ,  H03K17/0826

Abstract: Voltage/current characteristics control circuit particularly for protecting power transistors, which comprises at least one power transistor; the emitter terminal of a first transistor is directly connected to the output of the power transistor; the emitter terminal of a second transistor is connected to the first terminal of the power transistor by means of a first resistor. The collector terminal and the base terminal of the first transistor are connected to a current source. The base terminal of the first transistor is connected to the base terminal of the second transistor, and the circuit furthermore comprises a protection circuitry. The circuitry is connected to the collector terminal of the second transistor through a differential stage which comprises a third transistor and a fourth transistor; the third transistor and fourth transistor have a respective second resistor and third resistor arranged in series. Divider means are furthermore provided and are interposed between the second terminal of the power transistor and the base terminals of the third transistor and fourth transistor.

公开(公告)号：US5204638A

公开(公告)日：1993-04-20

申请号：US808492

申请日：1991-12-17

Applicant: Davide Brambilla ,  Fabrizio Stefani

Inventor： Davide Brambilla ,  Fabrizio Stefani

IPC: H03F3/34 ,  H03F3/343 ,  H03F3/45

CPC classification number: H03F3/45479 ,  H03F3/3437

Abstract: Intrinsic offset recovery circuit particularly for amplifiers, which comprises an input differential amplifier constituted by a first PNP transistor, by a second PNP transistor, by a third NPN transistor, by a fourth NPN transistor and by a first constant-current source, and a unitary-gain output stage. The recovery circuit furthermore comprises, as connection between the input differential amplifier and the unitary-gain output stage, a gain stage which comprises a fifth NPN transistor which is connected to the output of the input differential amplifier and is connected to a sixth NPN transistor and to a seventh PNP transistor. The seventh transistor is connected to the sixth transistor. The seventh transistor and the sixth transistor are connected to the unitary-gain output stage.

公开(公告)号：US20240131198A1

公开(公告)日：2024-04-25

申请号：US18225564

申请日：2023-07-24

Applicant: Davide Brambilla ,  Samuel Babity

Inventor： Davide Brambilla ,  Samuel Babity

IPC: A61K49/00 ,  A61M37/00

CPC classification number: A61K49/0032 ,  A61K49/0006 ,  A61K49/0054 ,  A61M37/0015 ,  A61M2037/0061

Abstract: The present disclosure relates to ratiometric detection compositions comprising a reference dye and a sensor dye that are PEGylated dyes, and microneedles comprising said compositions. The present disclosure further relates to methods of ratiometric detection/measurement/monitoring of analytes in a subject using the ratiometric detection compositions of the present disclosure.

公开(公告)号：US06437606B1

公开(公告)日：2002-08-20

申请号：US09687145

申请日：2000-10-13

Applicant: Danilo Ranieri ,  Davide Brambilla ,  Edoardo Botti ,  Luca Celant

Inventor： Danilo Ranieri ,  Davide Brambilla ,  Edoardo Botti ,  Luca Celant

IPC: H03K522

CPC classification number: H03F1/52

Abstract: A method of assessing the offset on the output nodes of an amplifying channel includes generating a logic signal for signaling the existence of an offset having a level exceeding a window of permitted levels symmetric about the zero level. The window is defined by a negative limit value and by a positive limit value. The method includes establishing an interval or phase of detection by applying to an input of a detection circuit a timing pulse with a certain frequency, sensing the rising edge of the timing pulse and setting a bistable circuit, and comparing the signal on the output nodes of the amplifiers channel with the window of permitted values. The bistable circuit is reset upon the occurrence, after the initial setting, of an output signal amplitude within the window of permitted values. Failure of the bistable circuit to reset before the end of the detection phase signals an excessive offset.

Abstract translation: 评估放大信道的输出节点上的偏移量的方法包括：生成逻辑信号，用于发信号通知具有超过关于零电平对称的允许电平的窗口的电平的偏移的存在。 窗口由负极限值和正极限值定义。 该方法包括通过向检测电路的输入施加具有一定频率的定时脉冲，感测定时脉冲的上升沿并设置双稳态电路，建立检测的间隔或相位，并将输出节点上的信号进行比较 放大器通道与允许值的窗口。 在初始设置之后，双稳态电路在允许值的窗口内的输出信号幅度出现之后被复位。 双稳态电路在检测阶段结束之前复位的故障发出过大的偏移。

公开(公告)号：US06429741B2

公开(公告)日：2002-08-06

申请号：US09880638

申请日：2001-06-12

Applicant: Davide Brambilla ,  Daniela Nebuloni ,  Mauro Cleris

Inventor： Davide Brambilla ,  Daniela Nebuloni ,  Mauro Cleris

IPC: H03F126

CPC classification number: H03F1/3217 ,  H03F1/34

Abstract: An amplifier having an input; an output supplying an output signal, and a feedback network connected between the input and the output, and a distortion detection circuit. The feedback network includes a first and a second feedback element arranged in series and forming an intermediate node supplying an intermediate signal in phase with the output signal in absence of distortion, and in phase-opposition with the output signal in presence of distortion. The distortion detection circuit includes a phase-comparating circuit which detects the phase of the output signal and of the intermediate signal, and generates a distortion-indicative signal, when the intermediate signal is in phase opposition with respect to the output signal.

Abstract translation: 具有输入的放大器; 提供输出信号的输出和连接在输入和输出之间的反馈网络，以及失真检测电路。 反馈网络包括串联布置的第一和第二反馈元件，并且形成中间节点，在没有失真的情况下提供与输出信号同相的中间信号，并且在存在失真的情况下与输出信号相反。 失真检测电路包括相位比较电路，当相对于输出信号相位相反时，相位比较电路检测输出信号和中间信号的相位，并产生失真指示信号。

公开(公告)号：US06392393B1

公开(公告)日：2002-05-21

申请号：US09594244

申请日：2000-06-15

Applicant: Davide Brambilla ,  Giovanni Capodivacca ,  Danilo Ranieri

Inventor： Davide Brambilla ,  Giovanni Capodivacca ,  Danilo Ranieri

IPC: G05F316

CPC classification number: H03F3/3071 ,  H03F1/52 ,  H03F3/50

Abstract: A method of voltage driving a load using a controlled current includes providing a negative feedback of an output current, measuring the output current on a collector of an output transistor of an output stage, comparing the measured output current with an input current to define a current difference, and providing the current difference at a base of the output transistor to provide the voltage driving.

Abstract translation: 使用受控电流对负载进行电压驱动的方法包括提供输出电流的负反馈，测量输出级的输出晶体管的集电极上的输出电流，将测得的输出电流与输入电流进行比较以限定电流 并且在输出晶体管的基极处提供电流差以提供电压驱动。