公开(公告)号：US5804460A

公开(公告)日：1998-09-08

申请号：US931066

申请日：1997-09-15

申请人： Jeffrey Bruce Bindell ,  Dennis Earl Schrope ,  Fred Anthony Stevie ,  Richard J. Dare ,  Larry E. Plew

发明人： Jeffrey Bruce Bindell ,  Dennis Earl Schrope ,  Fred Anthony Stevie ,  Richard J. Dare ,  Larry E. Plew

IPC分类号： G01Q40/02 ,  H01L21/66 ,  G01D18/00 ,  G06K9/28

CPC分类号： H01L22/20 ,  H01L22/12 ,  Y10S977/852 ,  Y10S977/86 ,  Y10S977/869 ,  Y10S977/881 ,  Y10S977/888

摘要： Illustratively, the present invention includes a method of integrated circuit manufacturing which includes forming a raised topological feature upon a first substrate. A portion of the raised feature is removed, thereby exposing a cross sectional view of the raised feature with the substrate remaining substantially undamaged. The cross sectional view has a critical dimension. The critical dimension of the cross sectional view is measured using a first measuring instrument. Then the critical dimension is measured using a second measuring instrument. The measurements of the first and second measuring instruments are correlated. Then, using the second measuring instrument, raised features via plurality of second substrates are measured.

摘要翻译： 说明性地，本发明包括集成电路制造方法，其包括在第一基板上形成凸起的拓扑特征。 升高的部分的一部分被去除，从而暴露凸​​起特征的横截面图，其中基底保持基本上未损坏。 截面图具有临界尺寸。 使用第一测量仪器测量横截面视图的临界尺寸。 然后使用第二测量仪器测量临界尺寸。 第一和第二测量仪器的测量值相关。 然后，使用第二测量仪器，测量经由多个第二基板的凸起特征。