公开(公告)号：US08107290B2

公开(公告)日：2012-01-31

申请号：US12078547

申请日：2008-04-01

申请人： Yoonmyung Lee ,  Michael John Wieckowski ,  David Theodore Blaauw ,  Dennis Michael Chen Sylvester

发明人： Yoonmyung Lee ,  Michael John Wieckowski ,  David Theodore Blaauw ,  Dennis Michael Chen Sylvester

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/0416 ,  G11C16/0441 ,  G11C2216/10 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11558 ,  H01L28/40

摘要： A memory cell structure for a memory device includes a read transistor having a floating gate node, a tunnelling capacitor, and a coupling capacitor stack. The tunnelling capacitor is connected to the floating gate node and has a first programming terminal, and the coupling capacitor stack is connected to the floating gate node and has a second programming terminal. The coupling capacitor stack includes at least two coupling capacitors arranged in series between the floating gate node and the second programming terminal, with the coupling capacitor stack having a larger capacitance than the tunnelling capacitor. Such a memory cell structure is efficient in terms of area, and can be manufactured using standard CMOS logic manufacturing processes, thereby avoiding some of the complexities involved in the production of conventional EEPROM and Flash memory devices.

摘要翻译： 用于存储器件的存储单元结构包括具有浮置栅极节点的读取晶体管，隧穿电容器和耦合电容器堆叠。 隧道电容器连接到浮动栅极节点并具有第一编程端子，耦合电容器堆叠连接到浮动栅极节点并具有第二编程端子。 耦合电容器堆叠包括串联布置在浮动栅极节点和第二编程端子之间的至少两个耦合电容器，耦合电容器堆叠具有比隧道电容器更大的电容。 这样的存储单元结构在面积上是有效的，并且可以使用标准CMOS逻辑制造工艺来制造，从而避免了常规EEPROM和闪存器件的生产中涉及的一些复杂性。

公开(公告)号：US20090244971A1

公开(公告)日：2009-10-01

申请号：US12078547

申请日：2008-04-01

申请人： Yoonmyung Lee ,  Michael John Wieckowski ,  David Theodore Blaauw ,  Dennis Michael Chen Sylvester

发明人： Yoonmyung Lee ,  Michael John Wieckowski ,  David Theodore Blaauw ,  Dennis Michael Chen Sylvester

IPC分类号： G11C16/06 ,  G11C11/24

CPC分类号： G11C16/0416 ,  G11C16/0441 ,  G11C2216/10 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11558 ,  H01L28/40

摘要： A memory cell structure for a memory device is provided, the memory cell structure comprising a read transistor having a floating gate node, a tunnelling capacitor, and a coupling capacitor stack. The tunnelling capacitor is connected to the floating gate node and has a first programming terminal, whilst the coupling capacitor stack is connected to the floating gate node and has a second programming terminal. The coupling capacitor stack comprises at least two coupling capacitors arranged in series between the floating gate node and the second programming terminal, with the coupling capacitor stack having a larger capacitance than the tunnelling capacitor. During a programming operation, a voltage difference is established between the first programming terminal and the second programming terminal to cause charge tunnelling to occur through the tunnelling capacitor, such that after the programming operation a charge is stored in the floating gate node. During a read operation, the read transistor is activated to produce an output signal indicative of the charge stored in the floating gate node. Such a memory cell structure is efficient in terms of area, and can be manufactured using standard CMOS logic manufacturing processes, thereby avoiding some of the complexities involved in the production of more conventional EEPROM and Flash memory devices.

摘要翻译： 提供了一种用于存储器件的存储单元结构，所述存储单元结构包括具有浮置栅极节点的读取晶体管，隧穿电容器和耦合电容器堆叠。 隧道电容器连接到浮动栅极节点并且具有第一编程端子，而耦合电容器堆叠件连接到浮动栅极节点并且具有第二编程端子。 耦合电容器堆叠包括串联布置在浮动栅极节点和第二编程端子之间的至少两个耦合电容器，耦合电容器堆叠具有比隧道电容器更大的电容。 在编程操作期间，在第一编程终端和第二编程终端之间建立电压差以通过隧穿电容器进行电荷隧穿，使得在编程操作之后，电荷被存储在浮动栅节点中。 在读取操作期间，读取晶体管被激活以产生指示存储在浮动栅极节点中的电荷的输出信号。 这样的存储单元结构在面积方面是有效的，并且可以使用标准CMOS逻辑制造工艺来制造，从而避免了生产更常规的EEPROM和闪存器件的一些复杂性。