公开(公告)号：US6055656A

公开(公告)日：2000-04-25

申请号：US434163

申请日：1995-05-02

申请人： James A. Wilson, Jr. ,  Anthony C. Miller ,  Michael W. Rhodehamel ,  Adrian Carbine ,  Derek B. I. Feltham ,  Sumeet Agrawal

发明人： James A. Wilson, Jr. ,  Anthony C. Miller ,  Michael W. Rhodehamel ,  Adrian Carbine ,  Derek B. I. Feltham ,  Sumeet Agrawal

IPC分类号： G01R31/3185 ,  G06F11/267 ,  G01R31/28

CPC分类号： G06F11/2236 ,  G01R31/318572

摘要： A scheme for accessing a control register bus and control registers of a microprocessor through a test access port which is configured to an established testing standard. A test access port (TAP) of a microprocessor is configured to communicate serially based on a technique specified in the IEEE 1149.1 standard. External serial instructions are converted for parallel transfer to provide control signals for accessing the internal structures. Serial address and data signals are also converted for parallel transfer to access internal structures on a control register bus and parallel outputs are converted to serial format for external output. By permitting external access to low level internal bus architecture, system testing and debug can be performed by utilizing external programming.

摘要翻译： 用于通过配置成建立的测试标准的测试访问端口访问控制寄存器总线和微处理器的控制寄存器的方案。 微处理器的测试访问端口（TAP）被配置为基于IEEE 1149.1标准中规定的技术来串行地进行通信。 外部串行指令被转换为并行传输，以提供用于访问内部结构的控制信号。 串行地址和数据信号也被转换为并行传输以访问控制寄存器总线上的内部结构，并行输出转换为用于外部输出的串行格式。 通过允许外部访问低级内部总线架构，可以通过利用外部编程来执行系统测试和调试。