公开(公告)号：US07672315B2

公开(公告)日：2010-03-02

申请号：US11210127

申请日：2005-08-23

Applicant: Dinesh Gupta ,  Dev Shankar Mukherjee ,  Rakesh Kumar Malik

Inventor： Dinesh Gupta ,  Dev Shankar Mukherjee ,  Rakesh Kumar Malik

IPC: H04L12/56

CPC classification number: H04J3/0623 ,  H04J3/1611 ,  H04J2203/0094

Abstract: Write logic and read logic are coupled to SDRAM and a frame status table. VCG members are written into SDRAM by the write logic and an entry (based on the MFI and SQ) in the frame status table is maintained by the write logic for each member. The read logic scans the frame status table to identify the earliest frame number for which data is available in SDRAM. Based on the frame status and the address pointer offset, the read logic maintains a state table entry for each VCG member and a state for each VCG. According to the preferred embodiment, the read logic is provided in two parts separated by a temporary buffer. The first part of the read logic performs the functions described above and writes chunk data into the temporary buffer. The second part of the read logic reads byte data from the temporary buffer according to a selectable leak rate.

Abstract translation: 写入逻辑和读取逻辑耦合到SDRAM和帧状态表。 VCG成员通过写逻辑写入SDRAM，帧状态表中的条目（基于MFI和SQ）由每个成员的写入逻辑维护。 读逻辑扫描帧状态表以识别SDRAM中数据可用的最早帧号。 基于帧状态和地址指针偏移，读逻辑维护每个VCG成员的状态表条目和每个VCG的状态。 根据优选实施例，读逻辑被提供在由临时缓冲器分开的两个部分中。 读逻辑的第一部分执行上述功能，并将块数据写入临时缓冲区。 读取逻辑的第二部分根据可选择的泄漏率从临时缓冲器读取字节数据。

公开(公告)号：US07558287B2

公开(公告)日：2009-07-07

申请号：US11210135

申请日：2005-08-23

Applicant: Rakesh Kumar Malik ,  Dev Shankar Mukherjee ,  Harsh Chilwal ,  Dinesh Gupta

Inventor： Rakesh Kumar Malik ,  Dev Shankar Mukherjee ,  Harsh Chilwal ,  Dinesh Gupta

IPC: H04L12/28 ,  H04J3/16

CPC classification number: H04J3/1611

Abstract: Combined hardware and software processing is applied in an end node of the network which includes mapping/demapping and deskewing. Most of the LCAS procedure is implemented in software so that it can be modified easily. Some of the procedure is implemented in hardware to meet stringent timing requirements. In particular, the handshaking protocol is implemented in software and the procedure for actually changing of the link capacity in response to the handshaking is implemented in hardware. The hardware and software communicate via a shared memory which includes a receive packet FIFO, receive control and status registers, a transmit packet FIFO, transmit control and status registers, and a transmit time slot interchange table.

Abstract translation: 组合的硬件和软件处理应用于网络的终端节点，包括映射/解映射和去歪斜。 大多数LCAS程序都是以软件实现的，因此可以轻松修改。 一些程序在硬件中实现以满足严格的时序要求。 特别地，握手协议在软件中实现，并且响应于握手实际改变链路容量的过程在硬件中实现。 硬件和软件通过包括接收分组FIFO，接收控制和状态寄存器，发送分组FIFO，发送控制和状态寄存器以及发送时隙交换表的共享存储器进行通信。

公开(公告)号：US20070047593A1

公开(公告)日：2007-03-01

申请号：US11210127

申请日：2005-08-23

Applicant: Dinesh Gupta ,  Dev Shankar Mukherjee ,  Rakesh Malik

Inventor： Dinesh Gupta ,  Dev Shankar Mukherjee ,  Rakesh Malik

IPC: H04J3/02

CPC classification number: H04J3/0623 ,  H04J3/1611 ,  H04J2203/0094

Abstract: Write logic and read logic are coupled to SDRAM and a frame status table. VCG members are written into SDRAM by the write logic and an entry (based on the MFI and SQ) in the frame status table is maintained by the write logic for each member. The read logic scans the frame status table to identify the earliest frame number for which data is available in SDRAM. Based on the frame status and the address pointer offset, the read logic maintains a state table entry for each VCG member and a state for each VCG. According to the preferred embodiment, the read logic is provided in two parts separated by a temporary buffer. The first part of the read logic performs the functions described above and writes chunk data into the temporary buffer. The second part of the read logic reads byte data from the temporary buffer according to a selectable leak rate.

Abstract translation: 写入逻辑和读取逻辑耦合到SDRAM和帧状态表。 VCG成员通过写逻辑写入SDRAM，帧状态表中的条目（基于MFI和SQ）由每个成员的写入逻辑维护。 读逻辑扫描帧状态表以识别SDRAM中数据可用的最早帧号。 基于帧状态和地址指针偏移，读逻辑维护每个VCG成员的状态表条目和每个VCG的状态。 根据优选实施例，读逻辑被提供在由临时缓冲器分开的两个部分中。 读逻辑的第一部分执行上述功能，并将块数据写入临时缓冲区。 读取逻辑的第二部分根据可选择的泄漏率从临时缓冲器读取字节数据。