公开(公告)号：US20080250364A1

公开(公告)日：2008-10-09

申请号：US11696724

申请日：2007-04-05

Applicant: Harsh Chilwal ,  Srikanth Jadcherla ,  Sriram Kotni ,  Prapanna Tiwari

Inventor： Harsh Chilwal ,  Srikanth Jadcherla ,  Sriram Kotni ,  Prapanna Tiwari

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F2217/78

Abstract: Multi-voltage circuit design verification segregates design elements into iso-voltage-rail blocks. Information on cross-over connections between the iso-voltage-rail blocks is obtained. Voltage effects are simulated in the circuit design, and, based on the cross-over information, the simulation results are modified. This yields more accurate results of simulations for multi-voltage circuit designs.

Abstract translation: 多电压电路设计验证将设计元件分为等电压轨块。 获得有关等电压轨块之间交叉连接的信息。 在电路设计中模拟电压效应，并根据交叉信息，对仿真结果进行了修改。 这为多电压电路设计产生更准确的模拟结果。

公开(公告)号：US07558287B2

公开(公告)日：2009-07-07

申请号：US11210135

申请日：2005-08-23

Applicant: Rakesh Kumar Malik ,  Dev Shankar Mukherjee ,  Harsh Chilwal ,  Dinesh Gupta

Inventor： Rakesh Kumar Malik ,  Dev Shankar Mukherjee ,  Harsh Chilwal ,  Dinesh Gupta

IPC: H04L12/28 ,  H04J3/16

CPC classification number: H04J3/1611

Abstract: Combined hardware and software processing is applied in an end node of the network which includes mapping/demapping and deskewing. Most of the LCAS procedure is implemented in software so that it can be modified easily. Some of the procedure is implemented in hardware to meet stringent timing requirements. In particular, the handshaking protocol is implemented in software and the procedure for actually changing of the link capacity in response to the handshaking is implemented in hardware. The hardware and software communicate via a shared memory which includes a receive packet FIFO, receive control and status registers, a transmit packet FIFO, transmit control and status registers, and a transmit time slot interchange table.

Abstract translation: 组合的硬件和软件处理应用于网络的终端节点，包括映射/解映射和去歪斜。 大多数LCAS程序都是以软件实现的，因此可以轻松修改。 一些程序在硬件中实现以满足严格的时序要求。 特别地，握手协议在软件中实现，并且响应于握手实际改变链路容量的过程在硬件中实现。 硬件和软件通过包括接收分组FIFO，接收控制和状态寄存器，发送分组FIFO，发送控制和状态寄存器以及发送时隙交换表的共享存储器进行通信。

公开(公告)号：US20090228852A1

公开(公告)日：2009-09-10

申请号：US12467955

申请日：2009-05-18

Applicant: Harsh Chilwal ,  Srikanth Jadcherla ,  Sriram Kotni ,  Prapanna Tiwari

Inventor： Harsh Chilwal ,  Srikanth Jadcherla ,  Sriram Kotni ,  Prapanna Tiwari

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F2217/78

Abstract: Multi-voltage circuit design verification segregates design elements into iso-voltage-rail blocks. Information on cross-over connections between the iso-voltage-rail blocks is obtained. Voltage effects are simulated in the circuit design, and, based on the cross-over information, the simulation results are modified. This yields more accurate results of simulations for multi-voltage circuit designs.

Abstract translation: 多电压电路设计验证将设计元件分为等电压轨块。 获得有关等电压轨块之间交叉连接的信息。 在电路设计中模拟电压效应，并根据交叉信息，对仿真结果进行了修改。 这为多电压电路设计产生更准确的模拟结果。

公开(公告)号：US07546566B2

公开(公告)日：2009-06-09

申请号：US11696724

申请日：2007-04-05

Applicant: Harsh Chilwal ,  Srikanth Jadcherla ,  Sriram Kotni ,  Prapanna Tiwari

Inventor： Harsh Chilwal ,  Srikanth Jadcherla ,  Sriram Kotni ,  Prapanna Tiwari

IPC: G06F17/50 ,  G06F9/45

CPC classification number: G06F17/5036 ,  G06F2217/78

Abstract: Multi-voltage circuit design verification segregates design elements into iso-voltage-rail blocks. Information on cross-over connections between the iso-voltage-rail blocks is obtained. Voltage effects are simulated in the circuit design, and, based on the cross-over information, the simulation results are modified. This yields more accurate results of simulations for multi-voltage circuit designs.

Abstract translation: 多电压电路设计验证将设计元件分为等电压轨块。 获得有关等电压轨块之间交叉连接的信息。 在电路设计中模拟电压效应，并根据交叉信息，对仿真结果进行了修改。 这为多电压电路设计产生更准确的模拟结果。

公开(公告)号：US08255859B2

公开(公告)日：2012-08-28

申请号：US12467955

申请日：2009-05-18

Applicant: Harsh Chilwal ,  Srikanth Jadcherla ,  Sriram Kotni ,  Prapanna Tiwari

Inventor： Harsh Chilwal ,  Srikanth Jadcherla ,  Sriram Kotni ,  Prapanna Tiwari

IPC: G06F17/50 ,  G06F9/455

CPC classification number: G06F17/5036 ,  G06F2217/78

Abstract: Multi-voltage circuit design verification segregates design elements into iso-voltage-rail blocks. Information on cross-over connections between the iso-voltage-rail blocks is obtained. Voltage effects are simulated in the circuit design, and, based on the cross-over information, the simulation results are modified. This yields more accurate results of simulations for multi-voltage circuit designs.

Abstract translation: 多电压电路设计验证将设计元件分为等电压轨块。 获得有关等电压轨块之间交叉连接的信息。 在电路设计中模拟电压效应，并根据交叉信息，对仿真结果进行了修改。 这为多电压电路设计产生更准确的模拟结果。

公开(公告)号：US20070047594A1

公开(公告)日：2007-03-01

申请号：US11210135

申请日：2005-08-23

Applicant: Rakesh Malik ,  Dev Mukherjee ,  Harsh Chilwal ,  Dinesh Gupta

Inventor： Rakesh Malik ,  Dev Mukherjee ,  Harsh Chilwal ,  Dinesh Gupta

IPC: H04L12/56

CPC classification number: H04J3/1611

Abstract: Combined hardware and software processing is applied in an end node of the network which includes mapping/demapping and deskewing. Most of the LCAS procedure is implemented in software so that it can be modified easily. Some of the procedure is implemented in hardware to meet stringent timing requirements. In particular, the handshaking protocol is implemented in software and the procedure for actually changing of the link capacity in response to the handshaking is implemented in hardware. The hardware and software communicate via a shared memory which includes a receive packet FIFO, receive control and status registers, a transmit packet FIFO, transmit control and status registers, and a transmit time slot interchange table.

Abstract translation: 组合的硬件和软件处理应用于网络的终端节点，包括映射/解映射和去歪斜。 大多数LCAS程序都是以软件实现的，因此可以轻松修改。 一些程序在硬件中实现以满足严格的时序要求。 特别地，握手协议在软件中实现，并且响应于握手实际改变链路容量的过程在硬件中实现。 硬件和软件通过包括接收分组FIFO，接收控制和状态寄存器，发送分组FIFO，发送控制和状态寄存器以及发送时隙交换表的共享存储器进行通信。