公开(公告)号：US20080034261A1

公开(公告)日：2008-02-07

申请号：US11457538

申请日：2006-07-14

申请人： Parag Birmiwal ,  Tilman Gloekler ,  Mack W. Riley ,  Devi Shanmugam ,  Polisetty V.N. Srinivas

发明人： Parag Birmiwal ,  Tilman Gloekler ,  Mack W. Riley ,  Devi Shanmugam ,  Polisetty V.N. Srinivas

IPC分类号： G01R31/28

CPC分类号： G01R31/318536

摘要： A system and method for reducing test time for loading and executing an architecture verification program for a system-on-a-chip (SoC) are provided. The mechanisms of the illustrative embodiments reorganize the scan chains of the SoC and provide an algorithm for organizing and pipelining architectural verification program (AVP) data for scanning into the reorganized scan chains. The scan chains are reorganized so as to align the scan cells for memory array data for each memory array across a plurality of scan chains. The scan chains are further reorganized so that each scan chain has unique AVP data, i.e. no scan chain has more than one memory array's information. The pipelining algorithm bundles data according to the length of the scan chain, the maximum size of the memory array data, and the position of the memory array's scan cells in the scan chains.

摘要翻译： 提供了一种用于减少用于加载和执行系统级芯片（SoC）的架构验证程序的测试时间的系统和方法。 说明性实施例的机制重新组织SoC的扫描链，并提供用于组织和流水线架构验证程序（AVP）数据的算法，用于扫描重组的扫描链。 扫描链被重组，以便对齐用于多个扫描链中的每个存储器阵列的存储器阵列数据的扫描单元。 扫描链进一步重组，使得每个扫描链具有唯一的AVP数据，即，没有扫描链具有多于一个的存储器阵列的信息。 流水线算法根据扫描链的长度，存储器阵列数据的最大大小以及扫描链中存储器阵列的扫描单元的位置来捆绑数据。

公开(公告)号：US07512925B2

公开(公告)日：2009-03-31

申请号：US11457538

申请日：2006-07-14

申请人： Parag Birmiwal ,  Tilman Gloekler ,  Mack W. Riley ,  Devi Shanmugam ,  Polisetty V. N. Srinivas

发明人： Parag Birmiwal ,  Tilman Gloekler ,  Mack W. Riley ,  Devi Shanmugam ,  Polisetty V. N. Srinivas

IPC分类号： G06F17/50 ,  G01R31/28 ,  G01R31/38

CPC分类号： G01R31/318536

摘要： A system and method for reducing test time for loading and executing an architecture verification program for a system-on-a-chip (SoC) are provided. The mechanisms of the illustrative embodiments reorganize the scan chains of the SoC and provide an algorithm for organizing and pipelining architectural verification program (AVP) data for scanning into the reorganized scan chains. The scan chains are reorganized so as to align the scan cells for memory array data for each memory array across a plurality of scan chains. The scan chains are further reorganized so that each scan chain has unique AVP data, i.e. no scan chain has more than one memory array's information. The pipelining algorithm bundles data according to the length of the scan chain, the maximum size of the memory array data, and the position of the memory array's scan cells in the scan chains.

摘要翻译： 提供了一种用于减少用于加载和执行系统级芯片（SoC）的架构验证程序的测试时间的系统和方法。 说明性实施例的机制重新组织SoC的扫描链，并提供用于组织和流水线架构验证程序（AVP）数据的算法，用于扫描重组的扫描链。 扫描链被重组，以便对齐用于多个扫描链中的每个存储器阵列的存储器阵列数据的扫描单元。 扫描链进一步重组，使得每个扫描链具有唯一的AVP数据，即，没有扫描链具有多于一个的存储器阵列的信息。 流水线算法根据扫描链的长度，存储器阵列数据的最大大小以及扫描链中存储器阵列的扫描单元的位置来捆绑数据。