公开(公告)号：US06661053B2

公开(公告)日：2003-12-09

申请号：US10022654

申请日：2001-12-18

申请人： Josef Willer ,  Frank Lau ,  Dezsö Takacs

发明人： Josef Willer ,  Frank Lau ,  Dezsö Takacs

IPC分类号： H01L2976

CPC分类号： H01L29/792 ,  H01L27/115 ,  H01L29/78

摘要： A memory cell includes a storage transistor having the following structure and being dimensioned to shorten program and erase times. A semiconductor body includes a top surface and a trench formed therein having walls joined by a curved bottom. A source zone in the semiconductor body is doped from the top surface. A drain zone in the semiconductor body is doped from the top surface. Junctions of the source and drain zones are beneath each. A gate electrode on the top surface of the semiconductor body is disposed between the source zone and the drain zone in the trench. A dielectric layer isolates the gate electrode from the semiconductor body and acts as a storage medium. Each of the junctions intersects a respective one of the walls at a respective depth from the bottom. A respective spacing across the trench is defined at each depth.

摘要翻译： 存储单元包括具有以下结构的存储晶体管，其尺寸被设计为缩短编程和擦除时间。 半导体本体包括顶表面和形成在其中的具有由弯曲底部连接的壁的沟槽。 半导体本体中的源区从顶表面掺杂。 半导体本体中的漏极区域从上表面掺杂。 源极和漏极区的接合点在每个下方。 半导体本体的顶表面上的栅电极设置在沟槽中的源区和漏区之间。 电介质层将栅电极与半导体本体隔离并用作存储介质。 每个连接点在与底部相应的深度处与相应的一个壁相交。 在每个深度处限定跨沟槽的相应间隔。