公开(公告)号：US06661053B2

公开(公告)日：2003-12-09

申请号：US10022654

申请日：2001-12-18

申请人： Josef Willer ,  Frank Lau ,  Dezsö Takacs

发明人： Josef Willer ,  Frank Lau ,  Dezsö Takacs

IPC分类号： H01L2976

CPC分类号： H01L29/792 ,  H01L27/115 ,  H01L29/78

摘要： A memory cell includes a storage transistor having the following structure and being dimensioned to shorten program and erase times. A semiconductor body includes a top surface and a trench formed therein having walls joined by a curved bottom. A source zone in the semiconductor body is doped from the top surface. A drain zone in the semiconductor body is doped from the top surface. Junctions of the source and drain zones are beneath each. A gate electrode on the top surface of the semiconductor body is disposed between the source zone and the drain zone in the trench. A dielectric layer isolates the gate electrode from the semiconductor body and acts as a storage medium. Each of the junctions intersects a respective one of the walls at a respective depth from the bottom. A respective spacing across the trench is defined at each depth.

摘要翻译： 存储单元包括具有以下结构的存储晶体管，其尺寸被设计为缩短编程和擦除时间。 半导体本体包括顶表面和形成在其中的具有由弯曲底部连接的壁的沟槽。 半导体本体中的源区从顶表面掺杂。 半导体本体中的漏极区域从上表面掺杂。 源极和漏极区的接合点在每个下方。 半导体本体的顶表面上的栅电极设置在沟槽中的源区和漏区之间。 电介质层将栅电极与半导体本体隔离并用作存储介质。 每个连接点在与底部相应的深度处与相应的一个壁相交。 在每个深度处限定跨沟槽的相应间隔。

公开(公告)号：US07087500B2

公开(公告)日：2006-08-08

申请号：US10894348

申请日：2004-07-19

申请人： Frank Lau ,  Josef Willer

发明人： Frank Lau ,  Josef Willer

IPC分类号： H01L21/76

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/792

摘要： A memory cell includes a channel region between source/drain regions at the top side of a semiconductor body and is provided, transversely with respect to the longitudinal direction, with a bulge formed in the semiconductor material. This results in a uniform distribution of the strength of a radially directed electric field and avoids field strength spikes at lateral edges of the channel region. A storage layer sequence is situated between the channel region and the gate electrode as part of a word line.

摘要翻译： 存储单元包括在半导体本体的顶侧的源极/漏极区之间的沟道区，并且相对于纵向方向横向地设置有形成在半导体材料中的凸起。 这导致径向电场的强度的均匀分布，并且避免了在通道区​​域的横向边缘处的场强尖峰。 存储层序列位于通道区域和栅电极之间，作为字线的一部分。

公开(公告)号：US20050242388A1

公开(公告)日：2005-11-03

申请号：US10835390

申请日：2004-04-30

申请人： Josef Willer ,  Frank Lau

发明人： Josef Willer ,  Frank Lau

IPC分类号： G11C16/02 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/76 ,  H01L29/786

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L29/66818 ,  H01L29/7851 ,  H01L29/78645

摘要： The present invention relates to a flash memory cell comprising a silicon substrate having an active region comprising a channel region and source-/drain-regions, the active region comprising a projecting portion, which projecting portion at least comprising said channel region; a tunneling dielectric layer formed on the surface of said active region; a floating gate formed on the surface of said tunneling dielectric layer for storing electric charges; an inter-gates coupling dielectric layer formed on the surface of said floating gate, and a control gate formed on the surface of said inter-gates coupling dielectric layer, wherein said floating gate is formed to have a groove-like shape for at least partly encompassing said projecting portion of said active region. This invention further relates to a flash memory device comprising such flash memory cells, as well as a manufacturing method thereof.

摘要翻译： 本发明涉及一种闪存单元，其包括具有包括沟道区和源 - 漏区的有源区的硅衬底，所述有源区包括突出部分，所述突出部分至少包括所述沟道区; 形成在所述有源区的表面上的隧道电介质层; 形成在用于存储电荷的所述隧道介电层的表面上的浮动栅极; 形成在所述浮置栅极的表面上的栅极间耦合电介质层和形成在所述栅极间耦合电介质层的表面上的控制栅极，其中所述浮动栅极形成为具有至少部分地具有沟槽形状 包围所述有源区域的所述突出部分。 本发明还涉及一种包括这种闪存单元的闪速存储器件及其制造方法。

公开(公告)号：US07087950B2

公开(公告)日：2006-08-08

申请号：US10835390

申请日：2004-04-30

申请人： Josef Willer ,  Frank Lau

发明人： Josef Willer ,  Frank Lau

IPC分类号： H01L29/76 ,  H01L29/788

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L29/66818 ,  H01L29/7851 ,  H01L29/78645

摘要： The present invention relates to a flash memory cell comprising a silicon substrate having an active region comprising a channel region and source-/drain-regions, the active region comprising a projecting portion, which projecting portion at least comprising said channel region; a tunneling dielectric layer formed on the surface of said active region; a floating gate formed on the surface of said tunneling dielectric layer for storing electric charges; an inter-gates coupling dielectric layer formed on the surface of said floating gate, and a control gate formed on the surface of said inter-gates coupling dielectric layer, wherein said floating gate is formed to have a groove-like shape for at least partly encompassing said projecting portion of said active region. This invention further relates to a flash memory device comprising such flash memory cells, as well as a manufacturing method thereof.

摘要翻译： 本发明涉及一种闪存单元，其包括具有包括沟道区和源 - 漏区的有源区的硅衬底，所述有源区包括突出部分，所述突出部分至少包括所述沟道区; 形成在所述有源区的表面上的隧道电介质层; 形成在用于存储电荷的所述隧道介电层的表面上的浮动栅极; 形成在所述浮置栅极的表面上的栅极间耦合电介质层和形成在所述栅极间耦合电介质层的表面上的控制栅极，其中所述浮动栅极形成为具有至少部分地具有沟槽形状 包围所述有源区域的所述突出部分。 本发明还涉及一种包括这种闪存单元的闪速存储器件及其制造方法。

公开(公告)号：US20050045963A1

公开(公告)日：2005-03-03

申请号：US10894348

申请日：2004-07-19

申请人： Frank Lau ,  Josef Willer

发明人： Frank Lau ,  Josef Willer

IPC分类号： H01L21/8246 ,  H01L27/115 ,  H01L29/423 ,  H01L29/792 ,  G11C11/34

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/792

摘要： A memory cell includes a channel region between source/drain regions at the top side of a semiconductor body and is provided, transversely with respect to the longitudinal direction, with a bulge formed in the semiconductor material. This results in a uniform distribution of the strength of a radially directed electric field and avoids field strength spikes at lateral edges of the channel region. A storage layer sequence is situated between the channel region and the gate electrode as part of a word line.

摘要翻译： 存储单元包括在半导体本体的顶侧的源/漏区之间的沟道区，并且相对于纵向方向横向地设置有形成在半导体材料中的凸起。 这导致径向电场的强度的均匀分布，并且避免了在通道区​​域的横向边缘处的场强尖峰。 存储层序列位于通道区域和栅电极之间，作为字线的一部分。

公开(公告)号：US20100019345A1

公开(公告)日：2010-01-28

申请号：US12177930

申请日：2008-07-23

申请人： Josef Willer ,  Michael Specht ,  Christoph Friederich ,  Doris Keitel-Schulz

发明人： Josef Willer ,  Michael Specht ,  Christoph Friederich ,  Doris Keitel-Schulz

IPC分类号： H01L21/3065 ,  H01L23/58

CPC分类号： H01L21/28273 ,  H01L21/3086 ,  H01L21/32139 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/7881

摘要： An integrated circuit is described. The integrated circuit may have: an active area line formed of a material of a semiconductor substrate with a first longitudinal direction parallel to an upper surface of the semiconductor substrate; wherein the active area line has at least one form-supporting element extending in a second longitudinal direction parallel to the upper surface of the semiconductor substrate; and wherein the second longitudinal direction is arranged with regard to the first longitudinal direction in an angle unequal to 0 degree and unequal to 180 degree.

摘要翻译： 描述了集成电路。 集成电路可以具有：由具有与半导体衬底的上表面平行的第一纵向方向的半导体衬底的材料形成的有源区线; 其中所述有源面积线具有至少一个形状支撑元件，所述支撑元件在平行于所述半导体衬底的上表面的第二纵向方向上延伸; 并且其中所述第二纵向方向相对于所述第一纵向方向以不等于0度并且不等于180度的角度布置。

公开(公告)号：US20090261397A1

公开(公告)日：2009-10-22

申请号：US12104750

申请日：2008-04-17

申请人： Josef Willer ,  Franz Hofmann ,  Michael Specht ,  Christoph Friederich ,  Doris Keitel-Schulz ,  Lars Bach ,  Thomas Melde

发明人： Josef Willer ,  Franz Hofmann ,  Michael Specht ,  Christoph Friederich ,  Doris Keitel-Schulz ,  Lars Bach ,  Thomas Melde

IPC分类号： H01L27/115 ,  H01L21/8247

CPC分类号： H01L27/11521

摘要： An integrated circuit is described. The integrated circuit may comprise a multitude of floating-gate electrodes, wherein at least one of the floating-gate electrodes has a lower width and an upper width, the lower width being larger than the upper width, and wherein the at least one of the floating-gate electrodes comprises a transition metal. A corresponding manufacturing method for an integrated circuit is also described.

摘要翻译： 描述了集成电路。 集成电路可以包括多个浮栅电极，其中浮栅电极中的至少一个具有较低宽度和上宽度，下宽度大于上宽度，并且其中至少一个 浮栅电极包括过渡金属。 还描述了集成电路的相应制造方法。

公开(公告)号：US07602649B2

公开(公告)日：2009-10-13

申请号：US11849828

申请日：2007-09-04

申请人： Josef Willer ,  Detlev Richter

发明人： Josef Willer ,  Detlev Richter

IPC分类号： G11C16/06

CPC分类号： G11C16/0483 ,  G11C16/26

摘要： In an embodiment of the invention, a method of operating an integrated circuit for reading the logical state of a selected one of a plurality of memory cells included within a memory cell string in the integrated circuit is provided.

摘要翻译： 在本发明的实施例中，提供了一种操作用于读取集成电路中的存储单元串中包括的多个存储单元中选定的一个的逻辑状态的集成电路的方法。

公开(公告)号：US20090251968A1

公开(公告)日：2009-10-08

申请号：US12099522

申请日：2008-04-08

申请人： Christoph Andreas Kleint ,  Josef Willer

发明人： Christoph Andreas Kleint ,  Josef Willer

IPC分类号： H01L21/00 ,  G11C16/04

CPC分类号： H01L27/11578 ,  H01L27/11582

摘要： In an embodiment, an integrated circuit may include a metallically conductive structure, a base structure having a crystal orientation, the base structure being adjacent to the metallically conductive structure, and a nanostructure disposed on the base structure, the nanostructure having substantially the same crystal orientation as the base structure.

摘要翻译： 在一个实施例中，集成电路可以包括金属导电结构，具有晶体取向的基底结构，与金属导电结构相邻的基底结构，以及设置在基底结构上的纳米结构，纳米结构具有基本上相同的晶体取向 作为基础结构。

公开(公告)号：US20090200533A1

公开(公告)日：2009-08-13

申请号：US12028513

申请日：2008-02-08

申请人： Klaus-Dieter Ufert ,  Josef Willer

发明人： Klaus-Dieter Ufert ,  Josef Willer

IPC分类号： H01L47/00 ,  H01L21/00

CPC分类号： H01L27/101 ,  H01L27/222 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/149 ,  H01L45/1625 ,  H01L45/1675

摘要： An integrated circuit including a memory cell and a method of manufacturing the integrated circuit are described. The memory cell includes a buried gate select transistor and a resistive memory element coupled to the buried gate select transistor. The resistive memory element stores information based on a resistivity of the resistive memory element.

摘要翻译： 描述了包括存储单元的集成电路和集成电路的制造方法。 存储单元包括掩埋栅极选择晶体管和耦合到掩埋栅选择晶体管的电阻存储元件。 电阻性存储元件基于电阻式存储元件的电阻率存储信息。