公开(公告)号：US20140036612A1

公开(公告)日：2014-02-06

申请号：US13567134

申请日：2012-08-06

申请人： Dharmendra Kumar Rai

发明人： Dharmendra Kumar Rai

IPC分类号： G11C5/14

CPC分类号： G11C11/417 ,  G11C5/147

摘要： A memory device having an array of memory cells and BTI-independent bias circuitry for controlling the bias voltage level of a source node of the array. The bias circuitry has an n-type transistor and a p-type transistor connected in parallel between ground and the source node. The bias circuitry also has circuitry for controlling the n-type and p-type transistors such that the memory device can be selectively configured in any of an active mode (where the source node is driven towards ground such that the array can be accessed), a low-leakage-current light sleep mode (where the source node is driven towards an intermediate, data-retention voltage level such that the array cannot be accessed but will retain data), and an even-lower-leakage-current shutdown mode (where the source node is driven towards the power supply voltage level such that the array cannot be accessed and cannot retain data).

摘要翻译： 一种存储器件，具有用于控制阵列的源节点的偏置电压电平的存储器单元阵列和与BTI无关的偏置电路。 偏置电路具有在地和源节点之间并联连接的n型晶体管和p型晶体管。 偏置电路还具有用于控制n型和p型晶体管的电路，使得存储器件可以被选择性地配置在任何主动模式（其中源节点被驱动到接地，使得阵列可被访问） 低泄漏电流光睡眠模式（其中源节点被驱动朝向中间的数据保持电压电平，使得阵列不能被访问但将保留数据）以及甚至更低的漏电流关断模式（ 其中源节点被驱动朝向电源电压电平，使得阵列不能被访问并且不能保留数据）。

公开(公告)号：US08462562B1

公开(公告)日：2013-06-11

申请号：US13300180

申请日：2011-11-18

申请人： Ankur Goel ,  Donald Albert Evans ,  Dennis Edward Dudeck ,  Richard John Stephani ,  Ronald James Wozniak ,  Dharmendra Kumar Rai ,  Rasoju Veerabadra Chary ,  Jeffrey Charles Herbert

发明人： Ankur Goel ,  Donald Albert Evans ,  Dennis Edward Dudeck ,  Richard John Stephani ,  Ronald James Wozniak ,  Dharmendra Kumar Rai ,  Rasoju Veerabadra Chary ,  Jeffrey Charles Herbert

IPC分类号： G11C7/20

CPC分类号： G11C5/146 ,  G11C5/147 ,  G11C11/412 ,  G11C11/417

摘要： A memory device comprises a memory block, a power gating transistor, and control circuitry. The memory block includes at least one memory cell comprising a storage element electrically connected to a source potential line, a drive strength of the storage element being a function of a voltage level on the source potential line. The power gating transistor, in turn, is connected between the source potential line and a voltage source. The control circuitry is operative to configure the power gating transistor to electrically connect the source potential line to the voltage source while the memory block is in a first mode, and to clamp the source potential line at a voltage different from that of the voltage source when the memory block is in a second mode.

摘要翻译： 存储器件包括存储器块，电源门控晶体管和控制电路。 存储块包括至少一个存储单元，其包括电连接到源极电位线的存储元件，存储元件的驱动强度是源极电位线上的电压电平的函数。 电源门控晶体管又连接在源极电位线和电压源之间。 控制电路用于配置功率门控晶体管，以在存储器块处于第一模式时将源极电位线电连接到电压源，并且将源极电位线钳位在与电压源不同的电压时， 存储器块处于第二模式。

公开(公告)号：US20130128676A1

公开(公告)日：2013-05-23

申请号：US13300180

申请日：2011-11-18

申请人： Ankur Goel ,  Donald Albert Evans ,  Dennis Edward Dudeck ,  Richard John Stephani ,  Ronald James Wozniak ,  Dharmendra Kumar Rai ,  Rasoju Veerabadra Chary ,  Jeffrey Charles Herbert

发明人： Ankur Goel ,  Donald Albert Evans ,  Dennis Edward Dudeck ,  Richard John Stephani ,  Ronald James Wozniak ,  Dharmendra Kumar Rai ,  Rasoju Veerabadra Chary ,  Jeffrey Charles Herbert

IPC分类号： G11C7/10

CPC分类号： G11C5/146 ,  G11C5/147 ,  G11C11/412 ,  G11C11/417

摘要： A memory device comprises a memory block, a power gating transistor, and control circuitry. The memory block includes at least one memory cell comprising a storage element electrically connected to a source potential line, a drive strength of the storage element being a function of a voltage level on the source potential line. The power gating transistor, in turn, is connected between the source potential line and a voltage source. The control circuitry is operative to configure the power gating transistor to electrically connect the source potential line to the voltage source while the memory block is in a first mode, and to clamp the source potential line at a voltage different from that of the voltage source when the memory block is in a second mode.

摘要翻译： 存储器件包括存储器块，电源门控晶体管和控制电路。 存储块包括至少一个存储单元，其包括电连接到源极电位线的存储元件，存储元件的驱动强度是源极电位线上的电压电平的函数。 电源门控晶体管又连接在源极电位线和电压源之间。 控制电路用于配置功率门控晶体管，以在存储器块处于第一模式时将源极电位线电连接到电压源，并且将源极电位线钳位在与电压源不同的电压时， 存储器块处于第二模式。