公开(公告)号：US20070156947A1

公开(公告)日：2007-07-05

申请号：US11323421

申请日：2005-12-29

申请人： Karthikeyan Vaithiananthan ,  Dharmin Parikh

发明人： Karthikeyan Vaithiananthan ,  Dharmin Parikh

IPC分类号： G06F12/06

CPC分类号： G06F12/1072 ,  G06F12/109 ,  G06F13/1668 ,  G06F2212/657

摘要： A method, device, and system are disclosed. In one embodiment, the method comprises mapping at least one bank in a memory to a first device for exclusive use, and mapping at least one other bank in the memory to a second device for exclusive use.

摘要翻译： 公开了一种方法，装置和系统。 在一个实施例中，该方法包括将存储器中的至少一个存储体映射到第一设备以供独占使用，以及将存储器中的至少一个其他存储体映射到第二设备以供专用。

公开(公告)号：US20070156946A1

公开(公告)日：2007-07-05

申请号：US11321273

申请日：2005-12-29

申请人： Sridhar Lakshmanamurthy ,  Dharmin Parikh ,  Karthik Vaithianathan ,  Gary Lavelle ,  Atul Kwatra

发明人： Sridhar Lakshmanamurthy ,  Dharmin Parikh ,  Karthik Vaithianathan ,  Gary Lavelle ,  Atul Kwatra

IPC分类号： G06F12/06 ,  G06F13/28

CPC分类号： G06F13/28 ,  G06F13/1631 ,  G06F13/1673

摘要： In some embodiments a memory controller is disclosed that includes at least one command/address input buffer to receive commands and addresses. The addresses specify a memory bank and a location within the memory bank An arbiter, coupled to the at least one command/address input buffer, merges commands and addresses from the at least one command/address input buffer and sorts the commands and addresses based on the addresses specified. A plurality of bank buffers, coupled to the arbiter and associated with memory banks, receive commands and addresses for their associated memory banks. A scheduler, coupled to the plurality of bank buffers, groups commands and addresses based on an examination of at least one command and address from the bank buffers. Other embodiments are otherwise disclosed herein.

摘要翻译： 在一些实施例中，公开了一种存储器控制器，其包括用于接收命令和地址的至少一个命令/地址输入缓冲器。 地址指定存储体和存储体内的位置耦合到至少一个命令/地址输入缓冲器的仲裁器从至少一个命令/地址输入缓冲器合并命令和地址，并根据 指定的地址。 耦合到仲裁器并与存储器组相关联的多个存储体缓冲器接收它们相关存储体的命令和地址。 基于对来自存储体缓冲器的至少一个命令和地址的检查，耦合到多个存储体缓冲器的调度器分组命令和地址。 其他实施例在此另外公开。