公开(公告)号：US06286128B1

公开(公告)日：2001-09-04

申请号：US09097299

申请日：1998-06-12

申请人： Lawrence Pileggi ,  Majid Sarrafzadeh ,  Sharad Malik ,  Abhijeet Chakraborty ,  Archie Li ,  Robert Eugene Shortt ,  Christopher Dunn ,  David Gluss ,  Dennis Yamamoto ,  Dinesh Gaitonde ,  Douglas B. Boyle ,  Emre Tuncer ,  Eric McCaughrin ,  Feroze Peshotan Taraporevala ,  Gary K. Yeap ,  James S. Koford ,  Joseph T. Rahmeh ,  Lilly Shieh ,  Salil R. Raje ,  Sam Jung Kim ,  Satamurthy Pullela ,  Yau-Tsun Steven Li ,  Tong Gao

发明人： Lawrence Pileggi ,  Majid Sarrafzadeh ,  Sharad Malik ,  Abhijeet Chakraborty ,  Archie Li ,  Robert Eugene Shortt ,  Christopher Dunn ,  David Gluss ,  Dennis Yamamoto ,  Dinesh Gaitonde ,  Douglas B. Boyle ,  Emre Tuncer ,  Eric McCaughrin ,  Feroze Peshotan Taraporevala ,  Gary K. Yeap ,  James S. Koford ,  Joseph T. Rahmeh ,  Lilly Shieh ,  Salil R. Raje ,  Sam Jung Kim ,  Satamurthy Pullela ,  Yau-Tsun Steven Li ,  Tong Gao

IPC分类号： G06F1750

CPC分类号： G06F17/505 ,  G06F17/5068 ,  G06F2217/78

摘要： A method for design optimization using logical and physical information is provided. In one embodiment, a method for design optimization using logical and physical information, includes receiving a behavioral description of an integrated circuit or a portion of an integrated circuit, optimizing placement of circuit elements in accordance with a first cost function, and optimizing logic of the circuit elements in accordance with a second cost function, in which the optimizing placement of the circuit elements and the optimizing logic of the circuit elements are performed concurrently. The method can further include optimizing routing in accordance with a third cost function, in which the optimizing routing, the optimizing placement of the circuit elements, and the optimizing logic of the circuit elements are performed concurrently.

摘要翻译： 提供了使用逻辑和物理信息进行设计优化的方法。 在一个实施例中，使用逻辑和物理信息的设计优化的方法包括接收集成电路或集成电路的一部分的行为描述，根据第一成本函数优化电路元件的布局，以及优化逻辑 根据第二成本函数的电路元件，其中同时执行电路元件的优化布置和电路元件的优化逻辑。 该方法可以进一步包括根据第三成本函数优化路由，其中​​同时执行优化路由，电路元件的优化布局和电路元件的优化逻辑。