公开(公告)号：US06449756B1

公开(公告)日：2002-09-10

申请号：US09094542

申请日：1998-06-12

Applicant: Sharad Malik ,  Lawrence Pileggi ,  Eric McCaughrin ,  Abhijeet Chakraborty ,  Douglas B. Boyle

Inventor： Sharad Malik ,  Lawrence Pileggi ,  Eric McCaughrin ,  Abhijeet Chakraborty ,  Douglas B. Boyle

IPC: G06F1750

CPC classification number: G06F17/5031

Abstract: A timing graph representing timing information of an integrated circuit design may change after modifications are made to the integrated circuit design. The modifications change timing parameters for edges in the timing graph. The measure of these changes may be computed at a computed measure compared to a threshold. In the event the measure exceeds the threshold, the edges in the timing graph that need to change in response to the modifications are updated. Otherwise, the current edges in the timing graph are continued to be used. The threshold is set in accordance with the accuracy and efficiency requirements of an electronic design automation tool.

Abstract translation: 表示集成电路设计的定时信息的时序图可以在对集成电路设计进行修改之后改变。 修改改变时序图中边缘的时序参数。 可以在与阈值相比较的计算措施下计算这些变化的度量。 在度量超过阈值的情况下，更新需要更改的时序图中的边缘。 否则，继续使用定时图中的当前边。 阈值是根据电子设计自动化工具的精度和效率要求设定的。

公开(公告)号：US06286128B1

公开(公告)日：2001-09-04

申请号：US09097299

申请日：1998-06-12

Applicant: Lawrence Pileggi ,  Majid Sarrafzadeh ,  Sharad Malik ,  Abhijeet Chakraborty ,  Archie Li ,  Robert Eugene Shortt ,  Christopher Dunn ,  David Gluss ,  Dennis Yamamoto ,  Dinesh Gaitonde ,  Douglas B. Boyle ,  Emre Tuncer ,  Eric McCaughrin ,  Feroze Peshotan Taraporevala ,  Gary K. Yeap ,  James S. Koford ,  Joseph T. Rahmeh ,  Lilly Shieh ,  Salil R. Raje ,  Sam Jung Kim ,  Satamurthy Pullela ,  Yau-Tsun Steven Li ,  Tong Gao

Inventor： Lawrence Pileggi ,  Majid Sarrafzadeh ,  Sharad Malik ,  Abhijeet Chakraborty ,  Archie Li ,  Robert Eugene Shortt ,  Christopher Dunn ,  David Gluss ,  Dennis Yamamoto ,  Dinesh Gaitonde ,  Douglas B. Boyle ,  Emre Tuncer ,  Eric McCaughrin ,  Feroze Peshotan Taraporevala ,  Gary K. Yeap ,  James S. Koford ,  Joseph T. Rahmeh ,  Lilly Shieh ,  Salil R. Raje ,  Sam Jung Kim ,  Satamurthy Pullela ,  Yau-Tsun Steven Li ,  Tong Gao

IPC: G06F1750

CPC classification number: G06F17/505 ,  G06F17/5068 ,  G06F2217/78

Abstract: A method for design optimization using logical and physical information is provided. In one embodiment, a method for design optimization using logical and physical information, includes receiving a behavioral description of an integrated circuit or a portion of an integrated circuit, optimizing placement of circuit elements in accordance with a first cost function, and optimizing logic of the circuit elements in accordance with a second cost function, in which the optimizing placement of the circuit elements and the optimizing logic of the circuit elements are performed concurrently. The method can further include optimizing routing in accordance with a third cost function, in which the optimizing routing, the optimizing placement of the circuit elements, and the optimizing logic of the circuit elements are performed concurrently.

Abstract translation: 提供了使用逻辑和物理信息进行设计优化的方法。 在一个实施例中，使用逻辑和物理信息的设计优化的方法包括接收集成电路或集成电路的一部分的行为描述，根据第一成本函数优化电路元件的布局，以及优化逻辑 根据第二成本函数的电路元件，其中同时执行电路元件的优化布置和电路元件的优化逻辑。 该方法可以进一步包括根据第三成本函数优化路由，其中​​同时执行优化路由，电路元件的优化布局和电路元件的优化逻辑。