公开(公告)号：US06614284B1

公开(公告)日：2003-09-02

申请号：US10011239

申请日：2001-11-08

申请人： Donald St. John Beeman ,  Jeffrey P. Kotowski

发明人： Donald St. John Beeman ,  Jeffrey P. Kotowski

IPC分类号： G06F764

CPC分类号： G06G7/62

摘要： A method and apparatus are directed to emulating an emitter follower with a small PNP transistor that is arranged in a PNP multiplier configuration. The PNP multiplier includes a PNP emitter follower and a current mirror. The PNP follower is coupled between the input and the output. A current mirror is coupled to the collector of the PNP follower such that mirror produces a current that is a scaled version of the collector current from the PNP follower. The current mirror is arranged to scale the PNP collector current by a factor of N. The effective output current from the PNP multiplier circuit corresponds to &bgr;·IIN·(N+1), where &bgr; corresponds to the large signal forward gain of the PNP follower. By multiplying the output current by a scaling factor, the effective forward gain of the PNP transistor is increased while utilizing a small geometry PNP device.

摘要翻译： 一种方法和装置涉及以PNP倍增器配置布置的小PNP晶体管来仿真射极跟随器。 PNP乘法器包括PNP发射极跟随器和电流镜。 PNP跟随器耦合在输入和输出之间。 电流镜耦合到PNP跟随器的集电极，使得反射镜产生电流，其是来自PNP跟随器的集电极电流的缩放版本。 电流镜被布置成将PNP集电极电流缩放N倍。来自PNP乘法器电路的有效输出电流对应于βIIN（N + 1），其中β对应于PNP的大信号正向增益 追随者 通过将输出电流乘以比例因子，PNP晶体管的有效正向增益增加，同时利用小几何PNP器件。

公开(公告)号：US06576977B1

公开(公告)日：2003-06-10

申请号：US10245022

申请日：2002-09-17

申请人： Donald St. John Beeman ,  Paul M. Werking

发明人： Donald St. John Beeman ,  Paul M. Werking

IPC分类号： H01L2976

CPC分类号： H01L29/66181 ,  H01L27/0733

摘要： An integrated dual-plate capacitor structure incorporates a small MOS transistor to reduce die area. The capacitor structure includes a semiconductor substrate having a first conductivity type and having a well region having a second conductivity type opposite the first conductivity type formed therein. An upper conductive plate and a lower conductive plate separated by a first layer of dielectric material are formed over the well region. The lower capacitor plate is separated from the upper surface of the well region by a second layer of dielectric material. A MOS transistor is formed in the semiconductor substrate. The MOS transistor includes space-apart source and drain regions of the second conductivity type that define a substrate channel region therebetween. A conductive gate is formed above the channel region and is separated therefrom by a layer of intervening dielectric material. The source region and the gate of the MOS transistor are connected to receive a bias voltage. The drain region of the MOS transistor is electrically connected to the well region. In an alternative embodiment, the drain of the MOS transistor is incorporated into the well region of the capacitor structure.

摘要翻译： 集成的双板电容器结构采用小型MOS晶体管，以减少管芯面积。 电容器结构包括具有第一导电类型并且具有与形成在其中的第一导电类型相反的第二导电类型的阱区的半导体衬底。 在阱区上形成由第一介电材料层隔开的上导电板和下导电板。 下电容器板通过第二介电材料层与阱区的上表面分离。 在半导体衬底中形成MOS晶体管。 MOS晶体管包括限定其间的衬底沟道区的第二导电类型的间隔开的源区和漏区。 导电栅极形成在沟道区上方，并通过中间介电材料层与其分离。 MOS晶体管的源极区域和栅极被连接以接收偏置电压。 MOS晶体管的漏极区电连接到阱区。 在替代实施例中，MOS晶体管的漏极被并入电容器结构的阱区。