公开(公告)号：US06794922B2

公开(公告)日：2004-09-21

申请号：US10081344

申请日：2002-02-20

申请人： Akira Mashimo

发明人： Akira Mashimo

IPC分类号： G06F764

CPC分类号： G06G7/186

摘要： A signal processing circuit outputs an output signal corresponding to a pulse width of an input pulse signal. This signal processing circuit comprises means for accumulating pulse widths of the input pulse signal for a predetermined period of time, and means for outputting the output signal corresponding to the accumulated pulse width. Each of these pulse widths has one of positive and negative polarities.

摘要翻译： 信号处理电路输出与输入脉冲信号的脉冲宽度对应的输出信号。 该信号处理电路包括用于在预定时间段内累积输入脉冲信号的脉冲宽度的装置，以及用于输出与累积脉冲宽度对应的输出信号的装置。 这些脉冲宽度中的每一个具有正极性和负极性之一。

公开(公告)号：US06781433B2

公开(公告)日：2004-08-24

申请号：US10421861

申请日：2003-04-24

申请人： Hiroyuki Mori

发明人： Hiroyuki Mori

IPC分类号： G06F764

CPC分类号： H03H11/1291

摘要： A first operational amplifier receives a reference voltage at one input terminal, a first transistor is connected between a first power source line and the first operational amplifier, a second transistor is connected between the first power source line and the first operational amplifier, a resistor is connected between the first transistor and a second power source line, a first switch is connected to the second transistor, a variable capacitor connected between the first switch and the second power source line, a second switch is connected the variable capacitor and the second power source line, a second operational amplifier is connected to the variable capacitor and the reference voltage, a third switch is connected to the second transistor, a load is connected between the third switch and the second power source line, and a control circuit is connected to the first to third switches.

摘要翻译： 第一运算放大器在一个输入端接收参考电压，第一晶体管连接在第一电源线与第一运算放大器之间，第二晶体管连接在第一电源线与第一运算放大器之间，电阻为 连接在第一晶体管和第二电源线之间，第一开关连接到第二晶体管，连接在第一开关和第二电源线之间的可变电容器，第二开关连接可变电容器和第二电源 第二运算放大器连接到可变电容器和参考电压，第三开关连接到第二晶体管，负载连接在第三开关和第二电源线之间，并且控制电路连接到 第一至第三开关。

公开(公告)号：US06777998B2

公开(公告)日：2004-08-17

申请号：US10216562

申请日：2002-08-09

申请人： Maurizio Zuffada ,  Giorgio Betti ,  Francesco Chrappan Soldavini ,  Martin Aureliano Hassner

发明人： Maurizio Zuffada ,  Giorgio Betti ,  Francesco Chrappan Soldavini ,  Martin Aureliano Hassner

IPC分类号： G06F764

CPC分类号： H03H11/481

摘要： An integrated electronic circuit includes a plurality of active circuits connected together in cascade. A feedback loop is between an output of a last active circuit and an input of a first active circuit so that the plurality of active devices function as a non-linear device, such as a capacitor. The integrated electronic circuit may be integrated or used in association with a circuit network including other non-linear devices.

摘要翻译： 集成电子电路包括级联连接在一起的多个有源电路。 反馈回路在最后一个有效电路的输出和第一有源电路的输入之间，使得多个有源器件用作诸如电容器之类的非线性器件。 集成电子电路可以与包括其他非线性装置的电路网络相关联地集成或使用。

公开(公告)号：US06476660B1

公开(公告)日：2002-11-05

申请号：US09362610

申请日：1999-07-28

申请人： Pasqualino Michelle Visocchi ,  Edward J W Whittaker ,  Robin M Flett

发明人： Pasqualino Michelle Visocchi ,  Edward J W Whittaker ,  Robin M Flett

IPC分类号： G06F764

CPC分类号： G06G7/186 ,  H03F3/087 ,  H03G3/3084 ,  H03G5/02

摘要： The present invention provides a long time constant integrator circuit as part of an integrated circuit. The integrator circuit is fully integrated on chip with no external capacitive or resistive components for enhancing the circuit's time constant. It achieves a −3 dB cut-off frequency of 1.6 Hz. The circuit is realisable on a very small area of silicon being formed by a bipolar process using npn transistors, resistive and capacitive elements. The integrator circuit comprises a transconductance stage as an input to an operational amplifier. The circuit design is fully differential and employs realisable resistors and capacitors.

摘要翻译： 本发明提供作为集成电路的一部分的长时间常数积分器电路。 积分器电路完全集成在芯片上，没有外部电容或电阻元件，以增强电路的时间常数。 它实现了1.6 Hz的-3 dB截止频率。 该电路可以在通过使用npn晶体管，电阻和电容元件的双极性工艺形成的非常小的硅区域上实现。 积分器电路包括跨导级作为运算放大器的输入。 电路设计是全差分的，并采用可实现的电阻和电容。

公开(公告)号：US06396329B1

公开(公告)日：2002-05-28

申请号：US09478914

申请日：2000-01-06

申请人： Jared L. Zerbe

发明人： Jared L. Zerbe

IPC分类号： G06F764

CPC分类号： H04L25/0276 ,  G11C7/02 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/1096 ,  G11C7/22 ,  G11C7/222 ,  G11C8/10 ,  H03K3/356034 ,  H03K5/131 ,  H03K5/133 ,  H03K17/162 ,  H03K19/00323 ,  H03K19/018528 ,  H03K2005/00065 ,  H03M5/20 ,  H04L7/0332 ,  H04L25/028 ,  H04L25/0292 ,  H04L25/03878

摘要： An apparatus and method for receiving high-speed signals having a wide common-mode range with low input-to-output latency. In one embodiment, the receiver includes an integrator to accumulate charge in accordance with an input signal during an integration time interval to produce an output voltage. A sense amplifier samples and converts the output voltage of the integrator to a logic signal; and a latch stores the logic signal. In an alternate embodiment, a preamplifier conditions the input signal prior to being integrated. In another embodiment using multiple receivers, circuitry is added to the receiver to compensate for timing errors associated with the distribution of the timing signals. In yet another embodiment, the integrator is coupled to an equalization circuit that compensates for intersymbol interference. In another embodiment, another circuit compensates for accumulated voltage offset errors in the integrator.

摘要翻译： 一种用于接收具有低输入到输出等待时间的宽共模范围的高速信号的装置和方法。 在一个实施例中，接收机包括积分器，以在积分时间间隔期间根据输入信号累积电荷以产生输出电压。 读出放大器对积分器的输出电压进行采样并转换为逻辑信号; 并且锁存器存储逻辑信号。 在替代实施例中，前置放大器在被积分之前调节输入信号。 在使用多个接收机的另一实施例中，将电路添加到接收机以补偿与定时信号的分布相关联的定时误差。 在另一个实施例中，积分器耦合到补偿符号间干扰的均衡电路。 在另一个实施例中，另一个电路补偿积分器中的累积电压偏移误差。

公开(公告)号：US06674317B1

公开(公告)日：2004-01-06

申请号：US10246275

申请日：2002-09-18

申请人： Shao Yu Chou

发明人： Shao Yu Chou

IPC分类号： G06F764

CPC分类号： H02M3/073

摘要： An output stage and method for a charge pump circuit which substantially reduces the degradation of the output voltage. A first NMOS transistor has its source connected to an input node and its drain connected to a second node. A second NMOS transistor has its source connected to the input node, its gate connected to the drain of the first NMOS transistor, and its drain connected to the gate of the first NMOS transistor. A capacitor is connected between a second clock signal and the drain of the second NMOS transistor. Another capacitor is connected between a first clock signal and an intermediate node. The key part of the invention is a diode pair connected anode of one to the cathode of the other and inserted between the intermediate node and the drain of the first NMOS transistor. This has the effect of changing a parallel combination of capacitors to a series combination of capacitors, thereby reducing the degradation of the output voltage and providing a stable voltage to the gate of an NMOS transistor switch in the output of the circuit.

摘要翻译： 用于电荷泵电路的输出级和方法，其基本上减少了输出电压的劣化。 第一NMOS晶体管的源极连接到输入节点，其漏极连接到第二节点。 第二NMOS晶体管的源极连接到输入节点，其栅极连接到第一NMOS晶体管的漏极，其漏极连接到第一NMOS晶体管的栅极。 电容器连接在第二时钟信号和第二NMOS晶体管的漏极之间。 另一电容器连接在第一时钟信号和中间节点之间。 本发明的关键部分是将一个阳极与另一个的阴极连接的二极管对，并且插入在第一NMOS晶体管的中间节点和漏极之间。 这具有将电容器的并联组合改变为电容器的串联组合的效果，从而减少输出电压的劣化并且向电路的输出中的NMOS晶体管开关的栅极提供稳定的电压。

公开(公告)号：US06614286B1

公开(公告)日：2003-09-02

申请号：US10171109

申请日：2002-06-11

申请人： Andrew T. K. Tang

发明人： Andrew T. K. Tang

IPC分类号： G06F764

CPC分类号： G06G7/184

摘要： An auto-ranging current integration circuit includes an operational amplifier which receives an input current to be integrated, and an array of integration capacitors which are switchably connected in parallel between the op amp's output and inverting input. A control circuit initially connects a first capacitor across the op amp, and then connects additional capacitors in parallel with the first whenever the op amp's output exceeds a predetermined voltage, but before the output becomes saturated. In this way, a smaller integration capacitance is automatically employed for a small input current, and larger capacitance values are automatically switched in for larger input currents, which lowers the integration gain, prevents the output from saturating, and keeps the current integration circuit's signal-to-noise ratio high.

摘要翻译： 自动量程电流积分电路包括接收待集成的输入电流的运算放大器和可操作地并联在运算放大器的输出和反相输入之间的积分电容器阵列。 控制电路最初连接运算放大器上的第一电容器，然后每当运算放大器的输出超过预定电压，但在输出饱和之前，连接附加电容器与第一电容器并联。 以这种方式，小的输入电流自动采用较小的积分电容，较大的输入电流自动切换较大的电容值，降低积分增益，防止输出饱和，并保持电流积分电路的信号 - 信噪比高。

公开(公告)号：US06614284B1

公开(公告)日：2003-09-02

申请号：US10011239

申请日：2001-11-08

申请人： Donald St. John Beeman ,  Jeffrey P. Kotowski

发明人： Donald St. John Beeman ,  Jeffrey P. Kotowski

IPC分类号： G06F764

CPC分类号： G06G7/62

摘要： A method and apparatus are directed to emulating an emitter follower with a small PNP transistor that is arranged in a PNP multiplier configuration. The PNP multiplier includes a PNP emitter follower and a current mirror. The PNP follower is coupled between the input and the output. A current mirror is coupled to the collector of the PNP follower such that mirror produces a current that is a scaled version of the collector current from the PNP follower. The current mirror is arranged to scale the PNP collector current by a factor of N. The effective output current from the PNP multiplier circuit corresponds to &bgr;·IIN·(N+1), where &bgr; corresponds to the large signal forward gain of the PNP follower. By multiplying the output current by a scaling factor, the effective forward gain of the PNP transistor is increased while utilizing a small geometry PNP device.

摘要翻译： 一种方法和装置涉及以PNP倍增器配置布置的小PNP晶体管来仿真射极跟随器。 PNP乘法器包括PNP发射极跟随器和电流镜。 PNP跟随器耦合在输入和输出之间。 电流镜耦合到PNP跟随器的集电极，使得反射镜产生电流，其是来自PNP跟随器的集电极电流的缩放版本。 电流镜被布置成将PNP集电极电流缩放N倍。来自PNP乘法器电路的有效输出电流对应于βIIN（N + 1），其中β对应于PNP的大信号正向增益 追随者 通过将输出电流乘以比例因子，PNP晶体管的有效正向增益增加，同时利用小几何PNP器件。

公开(公告)号：US06563364B2

公开(公告)日：2003-05-13

申请号：US10044039

申请日：2002-01-11

申请人： Jin-kuk Lee ,  Dong-young Chang ,  You-jin Cha ,  Geun-soon Kang ,  Seung-hoon Lee

发明人： Jin-kuk Lee ,  Dong-young Chang ,  You-jin Cha ,  Geun-soon Kang ,  Seung-hoon Lee

IPC分类号： G06F764

CPC分类号： H03G1/0094 ,  G06G7/06 ,  G06J1/00

摘要： A gain controller using switched capacitors is provided. The gain controller is operable in a sampling mode or an amplifying mode and controls the gain of an analog input signal. The gain controller includes an operational amplifier, input capacitors, a feedback capacitor, and switches. The operational amplifier controls the gain of the analog input signal and generates an output signal having the controlled gain. The input capacitors are connected to the input side of the operational amplifier in parallel. The feedback capacitor is connected between the input side and the output side of the operational amplifier. The switches connect at least one of the input capacitors to the input signal or a reference voltage, in response to the kinds of operation modes and a predetermined externally applied digital gain control signal. According to the gain controller using switched capacitors, it is possible to automatically control the gain of an input signal at high speed and to reduce power consumption since the time required for settling the gain of the input signal to a desired value is short.

公开(公告)号：US06407610B2

公开(公告)日：2002-06-18

申请号：US09751927

申请日：2000-12-29

申请人： Michelangelo Mazzucco ,  Vanni Poletto ,  Melano Carlo Lorenzo Protti

发明人： Michelangelo Mazzucco ,  Vanni Poletto ,  Melano Carlo Lorenzo Protti

IPC分类号： G06F764

CPC分类号： G01L23/225 ,  G06J1/00

摘要： A circuit extends the output voltage range of an integrator circuit wherein the input signal is used to produce an output signal, and the voltage of the output signal develops monotonically within a predetermined range of possible values. The integrator circuit is driven within an integration time period such that each time the signal at its output reaches a limit of the range of values, the integrator circuit starts a subsequent integration stage of the input signal in which the output signal develops again within the above-mentioned range. This takes place by resetting the integrator circuit or by a reversal of the characteristic slope of the output signal. This is combined with storing the number of occasions on which these interventions have occurred as determined by a scounter. This enables the actual voltage value of the signal resulting from the integration to be calculated by a relatively straightforward mathematical operation from the reading of the counter, and from the signal currently present at the output of the integrator at the end of the integration period.

摘要翻译： 电路扩展积分器电路的输出电压范围，其中输入信号用于产生输出信号，并且输出信号的电压在可能值的预定范围内单调发展。 积分电路在积分时间段内被驱动，使得每当其输出端的信号达到值范围的极限时，积分器电路开始输入信号的后续积分级，其中输出信号在上述范围内再次产生 提到的范围。 这通过复位积分器电路或反转输出信号的特性斜率来进行。 这与存储这些干预措施发生的场合的数量相结合，由扫描仪确定。 这使得通过来自计数器的读数的相对简单的数学运算以及在积分周期结束时当前存在于积分器的输出端的信号来计算由积分产生的信号的实际电压值。