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    Memory module test system with reduced driver output impedance
    9.
    发明授权
    Memory module test system with reduced driver output impedance 有权
    内存模块测试系统具有降低的驱动器输出阻抗

    公开(公告)号：US06442718B1

    公开(公告)日：2002-08-27

    申请号：US09378876

    申请日：1999-08-23

    申请人： Dong Tran ,  David Jeffrey ,  Steven C. Krow-Lucal

    发明人： Dong Tran ,  David Jeffrey ,  Steven C. Krow-Lucal

    IPC分类号： G11C2900

    CPC分类号： G11C29/56 ,  G01R31/31905 ,  G01R31/31924

    摘要： A memory module test system with reduced driver output impedance. A test system includes a plurality of driver circuits, each of which is coupled to a transmission line on a loadboard. The loadboard includes a socket for insertion of the memory module to be tested. A test signal is generated and driven onto a transmission line by a driver circuit. A duplicate test signal is driven by a separate driver circuit onto a separate transmission line. The transmission lines carrying the test signal and duplicate test signal are electrically shorted on the loadboard. Electrically shorting these transmission lines effectively reduces their impedance by half. Multiple test signals generated by the test system are shorted in this manner in order to allow the electrical environment of the test system to more closely approximate that of the application environment of the tested memory module.

    摘要翻译： 具有降低驱动器输出阻抗的存储器模块测试系统。 测试系统包括多个驱动器电路，每个驱动器电路耦合到装载板上的传输线。 该装载板包括用于插入要测试的存储器模块的插座。 通过驱动电路产生测试信号并将其驱动到传输线上。 重复的测试信号由单独的驱动器电路驱动到单独的传输线上。 承载测试信号和重复测试信号的传输线在电路板上电短路。 电气短路这些传输线有效地将其阻抗减少了一半。 测试系统生成的多个测试信号以这种方式被短路，以便允许测试系统的电气环境更接近测试存储器模块的应用环境。