公开(公告)号：US07363424B2

公开(公告)日：2008-04-22

申请号：US11619889

申请日：2007-01-04

申请人： Duane Rodney Aadsen ,  Dennis E. Dudeck ,  Donald A. Evans

发明人： Duane Rodney Aadsen ,  Dennis E. Dudeck ,  Donald A. Evans

IPC分类号： G06F12/00

CPC分类号： G11C15/00

摘要： Content addressable memories are disclosed that provide at least three states and are based on existing binary CAM devices. A higher order CAM having at least three states comprises a binary CAM having two binary bits; and a logic circuit to configure the two binary bits as a single CAM bit having said at least three states. The three states include a don't care state, a logic 0 state and a logic 1 state. The logic circuit may be embodied as two OR gates. The first match search (MS) input and a first wild card (WC) input of the higher order CAM are applied to inputs of the two OR gates and the outputs of the two OR gates are applied to the wild card (WC) inputs of the binary CAM. The match search (MS) inputs of the binary CAM are tied to a power supply voltage.

摘要翻译： 公开了提供至少三种状态并且基于现有的二进制CAM设备的内容可寻址存储器。 具有至少三个状态的高阶CAM包括具有两个二进制位的二进制CAM; 以及将所述两个二进制位配置为具有所述至少三个状态的单个CAM位的逻辑电路。 这三个状态包括无关状态，逻辑0状态和逻辑1状态。 逻辑电路可以被实现为两个OR门。 将高阶CAM的第一匹配搜索（MS）输入和第一通配符（WC）输入应用于两个或门的输入，并且两个或门的输出被施加到通配符（WC）输入的通配符 二进制CAM。 二进制CAM的匹配搜索（MS）输入与电源电压相关。

公开(公告)号：US07254763B2

公开(公告)日：2007-08-07

申请号：US10931709

申请日：2004-09-01

申请人： Duane Rodney Aadsen ,  Ilyoung I. Kim ,  Ross Alan Kohler ,  Richard Joseph McPartland

发明人： Duane Rodney Aadsen ,  Ilyoung I. Kim ,  Ross Alan Kohler ,  Richard Joseph McPartland

IPC分类号： G01R31/28

CPC分类号： G06F11/1008 ,  G01R31/3187 ,  G11C29/42

摘要： A memory self-testing system, apparatus, and method are provided which allow for testing for a plurality of bit errors and passing memory arrays having an error level which is correctable using selected error correction coding. An exemplary system embodiment includes a memory array, a comparator, an integrator, and a test control circuit. The memory array is adapted to store input test data and output stored test data during a plurality of memory read and write test operations. The comparator compares the input test data and the stored test data for a plurality of bit positions, and provides a corresponding error signal when the stored test data is not identical to the input test data for each bit position of the plurality of bit positions. The integrator receives the corresponding error signal and maintains the corresponding error signal for each bit position during the plurality of test operations. The test control circuit provides a fail signal when a predetermined level of corresponding error signals have been provided for the plurality of bit positions.

摘要翻译： 提供了一种存储器自检系统，装置和方法，其允许测试多个位错误并且传递具有使用所选择的纠错编码可校正的误差级别的存储器阵列。 示例性系统实施例包括存储器阵列，比较器，积分器和测试控制电路。 存储器阵列适于在多个存储器读写测试操作期间存储输入测试数据并输出存储的测试数据。 比较器比较多个比特位置的输入测试数据和存储的测试数据，并且当存储的测试数据与多个比特位置的每个比特位置的输入测试数据不相同时，提供相应的误差信号。 在多个测试操作期间，积分器接收对应的误差信号并维持每个比特位置的对应误差信号。 当为多个位位置提供预定水平的对应误差信号时，测试控制电路提供故障信号。

公开(公告)号：US07191280B2

公开(公告)日：2007-03-13

申请号：US10744798

申请日：2003-12-23

申请人： Duane Rodney Aadsen ,  Dennis E. Dudeck ,  Donald A. Evans

发明人： Duane Rodney Aadsen ,  Dennis E. Dudeck ,  Donald A. Evans

IPC分类号： G06F12/00

CPC分类号： G11C15/00

摘要： Content addressable memories are disclosed that provide at least three states and are based on existing binary CAM devices. A higher order CAM having at least three states comprises a binary CAM having two binary bits; and a logic circuit to configure the two binary bits as a single CAM bit having said at least three states. The three states include a don't care state, a logic 0 state and a logic 1 state. The logic circuit may be embodied as two OR gates. The first match search (MS) input and a first wild card (WC) input of the higher order CAM are applied to inputs of the two OR gates and the outputs of the two OR gates are applied to the wild card inputs of the binary CAM. The match search inputs of the binary CAM are tied to a power supply voltage.

摘要翻译： 公开了提供至少三种状态并且基于现有的二进制CAM设备的内容可寻址存储器。 具有至少三个状态的高阶CAM包括具有两个二进制位的二进制CAM; 以及将所述两个二进制位配置为具有所述至少三个状态的单个CAM位的逻辑电路。 这三个状态包括无关状态，逻辑0状态和逻辑1状态。 逻辑电路可以被实现为两个OR门。 高阶CAM的第一匹配搜索（MS）输入和第一通配符（WC）输入被应用于两个或门的输入，并且两个或门的输出被施加到二进制CAM的通配符输入 。 二进制CAM的匹配搜索输入与电源电压相关。