公开(公告)号：US06495399B1

公开(公告)日：2002-12-17

申请号：US09431238

申请日：1999-11-01

申请人： Shyue-Fong Quek ,  Ting Cheong Ang ,  Duay Ing Ong ,  Sang Yee Loong

发明人： Shyue-Fong Quek ,  Ting Cheong Ang ,  Duay Ing Ong ,  Sang Yee Loong

IPC分类号： H01L2150

CPC分类号： H01L23/3107 ,  H01L23/5221 ,  H01L23/5222 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor chip device package comprised of a semiconductor substrate having semiconductor devices formed on the semiconductor substrate. At least one dielectric layer is over the semiconductor substrate. At least one layer of interconnects is over the semiconductor devices and within the at least one respective dielectric layer with at least a portion of the interconnects being separated by voids having a vacuum or air therein. A passivation layer is over the uppermost of the at least one layer of interconnects. Wherein the semiconductor chip device is vacuum sealed within a semiconductor chip device package.

摘要翻译： 一种半导体芯片器件封装，包括形成在半导体衬底上的具有半导体器件的半导体衬底。 至少一个电介质层在半导体衬底之上。 至少一层互连在半导体器件之上，并且在至少一个相应的电介质层内，其中至少一部分互连由其中具有真空或空气的空隙分开。 钝化层位于至少一层互连层的最上面。 其中半导体芯片器件被真空密封在半导体芯片器件封装内。

公开(公告)号：US06737739B2

公开(公告)日：2004-05-18

申请号：US10283922

申请日：2002-10-30

申请人： Shyue-Fong Quek ,  Ting Cheong Ang ,  Duay Ing Ong ,  Sang Yee Loong

发明人： Shyue-Fong Quek ,  Ting Cheong Ang ,  Duay Ing Ong ,  Sang Yee Loong

IPC分类号： H01L2352

CPC分类号： H01L23/3107 ,  H01L23/5221 ,  H01L23/5222 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor chip device package comprised of a semiconductor substrate having semiconductor devices formed on the semiconductor substrate. At least one dielectric layer is over the semiconductor substrate. At least one layer of interconnects is over the semiconductor devices and within the at least one respective dielectric layer with at least a portion of the interconnects being separated by voids having a vacuum or air therein. A passivation layer is over the uppermost of the at least one layer of interconnects. Wherein the semiconductor chip device is vacuum sealed within a semiconductor chip device package.

摘要翻译： 一种半导体芯片器件封装，包括形成在半导体衬底上的具有半导体器件的半导体衬底。 至少一个电介质层在半导体衬底之上。 至少一层互连在半导体器件之上，并且在至少一个相应的电介质层内，其中至少一部分互连由其中具有真空或空气的空隙分开。 钝化层位于至少一层互连层的最上面。 其中半导体芯片器件被真空密封在半导体芯片器件封装内。