公开(公告)号：US10771187B1

公开(公告)日：2020-09-08

申请号：US16656937

申请日：2019-10-18

Applicant: Arm Limited ,  ECS Partners Limited

Inventor： Sahan Sajeewa Hiniduma Udugama Gamage ,  Benjamin James Fletcher ,  Shidhartha Das

IPC: H04L1/00 ,  H04L7/00 ,  H04B5/00

Abstract: A method and apparatus for transferring data maps the data to a modulation code using an encoder circuit having a configuration. A binary symbol of the data is mapped to a modulation code having a plurality of modulation digits and a modulation signal is generated based on the modulation code. A transmitter drive signal is modulated based on the modulation signal. A configuration of the encoder circuit is set based on a determined performance level. The transmitter drive signal may be used to produce an electromagnetic field by generating a positive, negative or zero electrical current in an induction coil of a first semiconductor die. A current induced by the electromagnetic field in an induction coil of a second semiconductor die is demodulated to recover the data whereby the data is transferred from the first semiconductor die to the second semiconductor die.

公开(公告)号：US20240028235A1

公开(公告)日：2024-01-25

申请号：US17813396

申请日：2022-07-19

Applicant: ECS Partners Limited ,  Arm Limited

Inventor： Sulaiman Sadiq ,  Jonathon Hare ,  Geoffrey Merrett ,  Partha Prasun Maji ,  Simon John Craske

IPC: G06F3/06

CPC classification number: G06F3/0644 ,  G06F3/0604 ,  G06F3/0673

Abstract: Briefly, embodiments, such as methods and/or systems for employing external memory devices in the execution of activation function such as activation functions implemented in a neural network. In one aspect, a first activation input tensor may be partitioned as a plurality of tensor segments stored in one or more external memory devices. Individual stored tensor segments may be sequentially loaded to memories local to processing circuitry to apply activation functions associated with the stored tensor segments.

公开(公告)号：US11366779B2

公开(公告)日：2022-06-21

申请号：US16685090

申请日：2019-11-15

Applicant: Arm Limited ,  ECS Partners Limited

Inventor： Benjamin James Fletcher ,  James Edward Myers ,  Shidhartha Das ,  Terrence Sui Tung Mak

IPC: G06F13/40 ,  H04L12/40

Abstract: A chip-carrier package includes a data processing system having one or more slave dies, a master die and a system bus. Each slave die includes a slave device and a slave-side wireless bus interface (WBI) coupled to the slave device. The master die includes a master device, one or more bus-side WBIs coupled to the master device. Each bus-side WBI is configured to be wirelessly coupled to at least one slave-side WBI of the one or more slave dies and a system bus. The system bus includes the one or more bus-side WBIs and the slave-side WBIs of the one or more slave-side dies. The system bus is configured to exchange information between the master device and the slave devices of the one or more slave dies.

公开(公告)号：US20240162936A1

公开(公告)日：2024-05-16

申请号：US18282899

申请日：2022-02-28

Applicant: Arm Limited ,  ECS Partners Limited

Inventor： Benjamin James Fletcher ,  James Edward Myers ,  Shidhartha Das ,  Sahan Sajeewa Hiniduma Udugama Gamage

IPC: H04B5/24 ,  H04L5/00

CPC classification number: H04B5/24 ,  H04L5/0007

Abstract: The present disclosure provides a method and apparatus for communicating between dice of an inductively-coupled 3D integrated circuit (3D-IC). A transmit resonant circuit at a transmit die is inductively coupled to a first receive resonant circuit at a first receive die, and to a second receive resonant circuit at a second receive die. The resonant circuit at the targeted receive die is tuned to the frequency of resonance of the transmit resonant circuit, while the resonant circuit at the untargeted receive die is detuned, resulting in lower power consumption for a given bit error rate at the targeted die.

公开(公告)号：US20210149834A1

公开(公告)日：2021-05-20

申请号：US16685090

申请日：2019-11-15

Applicant: Arm Limited ,  ECS Partners Limited

Inventor： Benjamin James Fletcher ,  James Edward Myers ,  Shidhartha Das ,  Terrence Sui Tung Mak

IPC: G06F13/40 ,  H04L12/40

Abstract: A chip-carrier package includes a data processing system having one or more slave dies, a master die and a system bus. Each slave die includes a slave device and a slave-side wireless bus interface (WBI) coupled to the slave device. The master die includes a master device, one or more bus-side WBIs coupled to the master device. Each bus-side WBI is configured to be wirelessly coupled to at least one slave-side WBI of the one or more slave dies and a system bus. The system bus includes the one or more bus-side WBIs and the slave-side WBIs of the one or more slave-side dies. The system bus is configured to exchange information between the master device and the slave devices of the one or more slave dies.