公开(公告)号：US20070237003A1

公开(公告)日：2007-10-11

申请号：US11398415

申请日：2006-04-05

Applicant: Ashot Melik-Martirosian ,  Ed Runnion ,  Mark Randolph ,  Meng Ding

Inventor： Ashot Melik-Martirosian ,  Ed Runnion ,  Mark Randolph ,  Meng Ding

IPC: G11C16/04

CPC classification number: G11C16/0475 ,  G11C16/12 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459

Abstract: A flash memory system configured in accordance with an example embodiment of the invention employs a virtual ground array architecture. During programming operations, target memory cells are biased with a positive source bias voltage to reduce or eliminate leakage current that might otherwise conduct through the target memory cells. A positive source bias voltage may also be applied to target memory cells during verification operations (program verify, soft program verify, erase verify) to reduce or eliminate leakage current that might otherwise introduce errors in the verification operations.

Abstract translation: 根据本发明的示例性实施例配置的闪存系统采用虚拟接地阵列架构。 在编程操作期间，目标存储器单元被偏置为正的源偏置电压，以减少或消除否则可能通过目标存储器单元传导的漏电流。 在验证操作（程序验证，软程序验证，擦除验证）期间，也可以将正源偏置电压施加到目标存储器单元，以减少或消除可能在验证操作中引入错误的泄漏电流。

公开(公告)号：US08031528B2

公开(公告)日：2011-10-04

申请号：US12557721

申请日：2009-09-11

Applicant: Ashot Melik-Martirosian ,  Ed Runnion ,  Mark Randolph ,  Meng Ding

Inventor： Ashot Melik-Martirosian ,  Ed Runnion ,  Mark Randolph ,  Meng Ding

IPC: G11C16/06 ,  G11C16/04

CPC classification number: G11C16/0475 ,  G11C16/12 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459

Abstract: A flash memory system configured in accordance with an example embodiment of the invention employs a virtual ground array architecture. During programming operations, target memory cells are biased with a positive source bias voltage to reduce or eliminate leakage current that might otherwise conduct through the target memory cells. A positive source bias voltage may also be applied to target memory cells during verification operations (program verify, soft program verify, erase verify) to reduce or eliminate leakage current that might otherwise introduce errors in the verification operations.

Abstract translation: 根据本发明的示例性实施例配置的闪存系统采用虚拟接地阵列架构。 在编程操作期间，目标存储器单元被偏置为正的源偏置电压，以减少或消除否则可能通过目标存储器单元传导的漏电流。 在验证操作（程序验证，软程序验证，擦除验证）期间，也可以将正源偏置电压施加到目标存储器单元，以减少或消除可能在验证操作中引入错误的泄漏电流。

公开(公告)号：US20100027350A1

公开(公告)日：2010-02-04

申请号：US12557721

申请日：2009-09-11

Applicant: Ashot MELIK-MARTIROSIAN ,  Ed RUNNION ,  Mark RANDOLPH ,  Meng DING

Inventor： Ashot MELIK-MARTIROSIAN ,  Ed RUNNION ,  Mark RANDOLPH ,  Meng DING

IPC: G11C16/06 ,  G11C7/00 ,  G11C16/04

CPC classification number: G11C16/0475 ,  G11C16/12 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459

Abstract: A flash memory system configured in accordance with an example embodiment of the invention employs a virtual ground array architecture. During programming operations, target memory cells are biased with a positive source bias voltage to reduce or eliminate leakage current that might otherwise conduct through the target memory cells. A positive source bias voltage may also be applied to target memory cells during verification operations (program verify, soft program verify, erase verify) to reduce or eliminate leakage current that might otherwise introduce errors in the verification operations.

Abstract translation: 根据本发明的示例性实施例配置的闪存系统采用虚拟接地阵列架构。 在编程操作期间，目标存储器单元被偏置为正的源偏置电压，以减少或消除否则可能通过目标存储器单元传导的漏电流。 在验证操作（程序验证，软程序验证，擦除验证）期间，也可以将正源偏置电压施加到目标存储器单元，以减少或消除可能在验证操作中引入错误的泄漏电流。

公开(公告)号：US07630253B2

公开(公告)日：2009-12-08

申请号：US11398415

申请日：2006-04-05

Applicant: Ashot Melik-Martirosian ,  Ed Runnion ,  Mark Randolph ,  Meng Ding

Inventor： Ashot Melik-Martirosian ,  Ed Runnion ,  Mark Randolph ,  Meng Ding

IPC: G11C16/04

CPC classification number: G11C16/0475 ,  G11C16/12 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459

Abstract: A flash memory system configured in accordance with an example embodiment of the invention employs a virtual ground array architecture. During programming operations, target memory cells are biased with a positive source bias voltage to reduce or eliminate leakage current that might otherwise conduct through the target memory cells. A positive source bias voltage may also be applied to target memory cells during verification operations (program verify, soft program verify, erase verify) to reduce or eliminate leakage current that might otherwise introduce errors in the verification operations.

Abstract translation: 根据本发明的示例性实施例配置的闪存系统采用虚拟接地阵列架构。 在编程操作期间，目标存储器单元被偏置为正的源偏置电压，以减少或消除否则可能通过目标存储器单元传导的漏电流。 在验证操作（程序验证，软程序验证，擦除验证）期间，也可以将正源偏置电压施加到目标存储器单元，以减少或消除可能在验证操作中引入错误的泄漏电流。