公开(公告)号：US08404541B2

公开(公告)日：2013-03-26

申请号：US12790578

申请日：2010-05-28

Applicant: Wei Zheng ,  Jean Yang ,  Mark Randolph ,  Ming Kwan ,  Yi He ,  Zhizheng Liu ,  Meng Ding

Inventor： Wei Zheng ,  Jean Yang ,  Mark Randolph ,  Ming Kwan ,  Yi He ,  Zhizheng Liu ,  Meng Ding

IPC: H01L21/8247

CPC classification number: H01L27/105 ,  H01L27/11526 ,  H01L27/11531

Abstract: A semiconductor device includes a substrate and a memory cell formed on the substrate. The memory cell includes a word line. The semiconductor device also includes a protection area formed in the substrate, a conductive structure configured to extend the word line to the protection area, and a contact configured to short the word line and the protection area.

Abstract translation: 半导体器件包括衬底和形成在衬底上的存储单元。 存储单元包括字线。 半导体器件还包括形成在衬底中的保护区域，被配置为将字线延伸到保护区域的导电结构以及被配置为使字线和保护区域短路的触点。

公开(公告)号：US08203178B2

公开(公告)日：2012-06-19

申请号：US12860074

申请日：2010-08-20

Applicant: Ashot Melik Martirosian ,  Zhizheng Liu ,  Mark Randolph

Inventor： Ashot Melik Martirosian ,  Zhizheng Liu ,  Mark Randolph

IPC: H01L21/336

CPC classification number: H01L21/76838 ,  H01L21/76816 ,  H01L27/11521

Abstract: A semiconductor device includes a substrate, a memory cell formed on the substrate, and a contact to the substrate. The contact is formed in an area away from the memory cell and functions to raise the potential of the substrate.

Abstract translation: 半导体器件包括衬底，形成在衬底上的存储单元和与衬底的接触。 接触形成在远离存储单元的区域中，起到提高衬底电位的作用。

公开(公告)号：US20110264236A1

公开(公告)日：2011-10-27

申请号：US13028725

申请日：2011-02-16

Applicant: Erik Bassett ,  Mack Cheney ,  Theresa Hadlock ,  Irina Pomerantseva ,  Mark Randolph ,  Cathryn Sundback ,  Joseph Vacanti

Inventor： Erik Bassett ,  Mack Cheney ,  Theresa Hadlock ,  Irina Pomerantseva ,  Mark Randolph ,  Cathryn Sundback ,  Joseph Vacanti

IPC: A61F2/02 ,  B29C39/10 ,  C12N11/14

CPC classification number: C12N5/0655 ,  A61L27/04 ,  A61L27/24 ,  A61L27/50 ,  C12N5/0663 ,  C12N2501/15 ,  C12N2502/1317 ,  C12N2533/54

Abstract: The present invention provides for compositions and constructs for craniofacial reconstruction implants, and methods for making and using same. Specific embodiments provide for a biocompatible scaffold having an auricular shape and a permanent bendable framework within the scaffold, wherein the permanent bendable framework allows deformation and return to pre-deformation shape, and thus maintains the auricular shape of the scaffold.

Abstract translation: 本发明提供了用于颅面重建植入物的组合物和构建体，以及制备和使用它们的方法。 具体实施方案提供了在支架内具有耳孔形状和永久可弯曲框架的生物相容性支架，其中永久可弯曲框架允许变形并返回到预变形形状，从而保持支架的耳形。

公开(公告)号：US07804125B2

公开(公告)日：2010-09-28

申请号：US11782507

申请日：2007-07-24

Applicant: Ashot Melik Martirosian ,  Zhizheng Liu ,  Mark Randolph

Inventor： Ashot Melik Martirosian ,  Zhizheng Liu ,  Mark Randolph

IPC: H01L21/336

CPC classification number: H01L21/76838 ,  H01L21/76816 ,  H01L27/11521

Abstract: A semiconductor device includes a substrate, a memory cell formed on the substrate, and a contact to the substrate. The contact is formed in an area away from the memory cell and functions to raise the potential of the substrate.

Abstract translation: 半导体器件包括衬底，形成在衬底上的存储单元和与衬底的接触。 接触形成在远离存储单元的区域中，起到提高衬底电位的作用。

公开(公告)号：US07713875B2

公开(公告)日：2010-05-11

申请号：US11748215

申请日：2007-05-14

Applicant: Michael Brennan ,  Yi He ,  Mark Randolph ,  Ming-Sang Kwan

Inventor： Michael Brennan ,  Yi He ,  Mark Randolph ,  Ming-Sang Kwan

IPC: H01L21/44

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L21/76837 ,  H01L27/115 ,  H01L29/7923

Abstract: The present invention facilitates memory devices and operation of dual bit and single bit memory devices by providing systems and methods that employ a salicide block to vary and equalize the resistance of a memory array during fabrication. The present invention includes utilizing a common charge dissipation region to mitigate charge-loss by providing protection against charging up of the various lines as a result of further plasma etching processes. The salicide block equalizes the charge dissipation in the memory array by providing each wordline path with a varied amount of resistance in addition to the total path resistance. Because the charge protection provided to each wordline otherwise varies depending on the resistance path to a common discharge element, a salicide block for resistance equalization provides greater reliability and predictability during processing. Other such shapes conducive for any desired resistance path fall within the scope of the invention.

Abstract translation: 本发明通过提供使用自对准硅化物块在制造期间改变和均衡存储器阵列的电阻的系统和方法来便利存储器件和双位和单位存储器件的操作。 本发明包括利用公共电荷消耗区域来减少电荷损耗，因为通过进一步的等离子体蚀刻工艺，提供了防止各种线路充电的保护。 除了总路径电阻之外，通过为每个字线路径提供不同量的电阻，自对准硅胶块均衡存储器阵列中的电荷耗散。 因为提供给每个字线的电荷保护还根据到公共放电元件的电阻路径而变化，所以用于电阻均衡的自对准硅化物块在处理期间提供更高的可靠性和可预测性。 有利于任何所需阻力路径的其它这种形状落在本发明的范围内。

公开(公告)号：US07671403B2

公开(公告)日：2010-03-02

申请号：US11567257

申请日：2006-12-06

Applicant: Wei Zheng ,  Chi Chang ,  Mark Randolph ,  Satoshi Torii

Inventor： Wei Zheng ,  Chi Chang ,  Mark Randolph ,  Satoshi Torii

IPC: H01L29/792

CPC classification number: H01L27/115 ,  H01L27/11568

Abstract: A device includes a substrate and multiple wells formed over the substrate and isolated from one another by dielectric trenches. The device further includes multiple memory elements formed over the wells, each of the memory elements extending approximately perpendicular to the wells and including a material doped with n-type impurities. The device also includes multiple source/drain regions, each source/drain region formed within one of multiple trenches and inside one of the plurality of wells between a pair of the memory elements, each of the source/drain regions implanted with p-type impurities. The device further includes a first substrate contact formed in a first one of the multiple trenches through a first one of the wells into the substrate and a second substrate contact formed in a second one of the multiple trenches through a second one of the wells into the substrate.

Abstract translation: 一种器件包括衬底和形成在衬底上并由电介质沟槽彼此隔离的多个阱。 该器件还包括形成在阱上的多个存储元件，每个存储元件大致垂直于阱延伸并且包括掺杂有n型杂质的材料。 器件还包括多个源极/漏极区域，每个源极/漏极区域形成在多个沟槽中的一个内，并且在一对存储元件之间的多个阱中的一个内部，源极/漏极区域中的每一个注入p型杂质 。 所述器件还包括形成在所述多个沟槽中的第一个沟槽中的第一衬底接触件，穿过所述衬底中的第一孔，以及形成在所述多个沟槽中的第二个沟槽中的第二衬底接触件中的第二衬底接触入第 基质。

公开(公告)号：US20080151590A1

公开(公告)日：2008-06-26

申请号：US11614053

申请日：2006-12-20

Applicant: David M. Rogers ,  Mimi X. Qian ,  Kwadwo A. Appiah ,  Mark Randolph ,  Michael A. VanBuskirk ,  Tazrien Kamal ,  Hiroyuki Kinoshita ,  Yi He ,  Wei Zheng

Inventor： David M. Rogers ,  Mimi X. Qian ,  Kwadwo A. Appiah ,  Mark Randolph ,  Michael A. VanBuskirk ,  Tazrien Kamal ,  Hiroyuki Kinoshita ,  Yi He ,  Wei Zheng

IPC: H01L23/60 ,  G11C5/00

CPC classification number: H01L21/768 ,  G11C8/08 ,  G11C8/14 ,  H01L27/0248 ,  H01L29/66477 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device (400) for improved charge dissipation protection includes a substrate (426), a layer of semiconductive or conductive material (406), one or more thin film devices (408) and a charge passage device (414). The thin film devices (408) are connected to the semiconductive or conductive layer (406) and the charge passage device (414) is coupled to the thin film devices (408) and to the substrate (426) and provides a connection from the thin film devices (408) to the substrate (426) to dissipate charge from the semiconductive/conductive layer (406) to the substrate (426).

Abstract translation: 用于改善电荷耗散保护的半导体器件（400）包括衬底（426），半导体或导电材料层（406），一个或多个薄膜器件（408）和电荷通道器件（414）。 薄膜器件（408）连接到半导体或导电层（406），并且电荷通道器件（414）耦合到薄膜器件（408）和衬底（426），并提供来自薄的 薄膜器件（408）到衬底（426）以将电荷从半导体/导电层（406）耗散到衬底（426）。

公开(公告)号：US20080150007A1

公开(公告)日：2008-06-26

申请号：US11748215

申请日：2007-05-14

Applicant: Michael Brennan ,  Yi He ,  Mark Randolph ,  Ming-Sang Kwan

Inventor： Michael Brennan ,  Yi He ,  Mark Randolph ,  Ming-Sang Kwan

IPC: H01L29/792 ,  H01L21/8239

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L21/76837 ,  H01L27/115 ,  H01L29/7923

Abstract: The present invention facilitates memory devices and operation of dual bit and single bit memory devices by providing systems and methods that employ a salicide block to vary and equalize the resistance of a memory array during fabrication. The present invention includes utilizing a common charge dissipation region to mitigate charge-loss by providing protection against charging up of the various lines as a result of further plasma etching processes. The salicide block equalizes the charge dissipation in the memory array by providing each wordline path with a varied amount of resistance in addition to the total path resistance. Because the charge protection provided to each wordline otherwise varies depending on the resistance path to a common discharge element, a salicide block for resistance equalization provides greater reliability and predictability during processing. Other such shapes conducive for any desired resistance path fall within the scope of the invention.

Abstract translation: 本发明通过提供使用自对准硅化物块在制造期间改变和均衡存储器阵列的电阻的系统和方法来便利存储器件和双位和单位存储器件的操作。 本发明包括利用公共电荷消耗区域来减少电荷损耗，因为通过进一步的等离子体蚀刻工艺，提供了防止各种线路充电的保护。 除了总路径电阻之外，通过为每个字线路径提供不同量的电阻，自对准硅胶块均衡存储器阵列中的电荷耗散。 因为提供给每个字线的电荷保护还根据到公共放电元件的电阻路径而变化，所以用于电阻均衡的自对准硅化物块在处理期间提供更高的可靠性和可预测性。 有利于任何所需阻力路径的其它这种形状落在本发明的范围内。

公开(公告)号：US20080135918A1

公开(公告)日：2008-06-12

申请号：US11567257

申请日：2006-12-06

Applicant: Wei Zheng ,  Chi Chang ,  Mark Randolph ,  Satoshi Torii

Inventor： Wei Zheng ,  Chi Chang ,  Mark Randolph ,  Satoshi Torii

IPC: H01L27/115

CPC classification number: H01L27/115 ,  H01L27/11568

Abstract: A device includes a substrate and multiple wells formed over the substrate and isolated from one another by dielectric trenches. The device further includes multiple memory elements formed over the wells, each of the memory elements extending approximately perpendicular to the wells and including a material doped with n-type impurities. The device also includes multiple source/drain regions, each source/drain region formed within one of multiple trenches and inside one of the plurality of wells between a pair of the memory elements, each of the source/drain regions implanted with p-type impurities. The device further includes a first substrate contact formed in a first one of the multiple trenches through a first one of the wells into the substrate and a second substrate contact formed in a second one of the multiple trenches through a second one of the wells into the substrate.

Abstract translation: 一种器件包括衬底和形成在衬底上并由电介质沟槽彼此隔离的多个阱。 该器件还包括形成在阱上的多个存储元件，每个存储元件大致垂直于阱延伸并且包括掺杂有n型杂质的材料。 器件还包括多个源极/漏极区域，每个源极/漏极区域形成在多个沟槽中的一个内，并且在一对存储元件之间的多个阱中的一个内部，源极/漏极区域中的每一个注入p型杂质 。 所述器件还包括形成在所述多个沟槽中的第一个沟槽中的第一衬底接触件，穿过所述衬底中的第一孔，以及形成在所述多个沟槽中的第二个沟槽中的第二衬底接触件中的第二衬底接触入第 基质。

公开(公告)号：US20070267686A1

公开(公告)日：2007-11-22

申请号：US11782507

申请日：2007-07-24

Applicant: Ashot MARTIROSIAN ,  Zhizheng Liu ,  Mark Randolph

Inventor： Ashot MARTIROSIAN ,  Zhizheng Liu ,  Mark Randolph

IPC: H01L29/788

CPC classification number: H01L21/76838 ,  H01L21/76816 ,  H01L27/11521

Abstract: A semiconductor device includes a substrate, a memory cell formed on the substrate, and a contact to the substrate. The contact is formed in an area away from the memory cell and functions to raise the potential of the substrate.

Abstract translation: 半导体器件包括衬底，形成在衬底上的存储单元和与衬底的接触。 接触形成在远离存储单元的区域中，起到提高衬底电位的作用。