公开(公告)号：US06026473A

公开(公告)日：2000-02-15

申请号：US771847

申请日：1996-12-23

申请人： Leonard W. Cross ,  Edward Paul Wallace

发明人： Leonard W. Cross ,  Edward Paul Wallace

IPC分类号： G06F5/16 ,  G06F13/16 ,  G06F12/00 ,  G06F13/00

CPC分类号： G06F5/16 ,  G06F13/1647

摘要： A method and apparatus for storing data values received within respective cycle periods of a clock signal are disclosed. Data values are alternately stored in first and second data hold registers and then output by each data hold register for a time greater than a cycle period of the clock signal. Address values at which the incoming data values are to be written are alternately stored in first and second address hold registers. Data stored in the first data hold register is written to a latch-based memory element in a first memory bank indicated by an address value stored in the first address hold register. Data stored in the second data hold register is written to a latch-based memory element in a second memory bank indicated by an address value stored in the second address hold register.

摘要翻译： 公开了一种用于存储在时钟信号的各个周期周期内接收的数据值的方法和装置。 数据值交替存储在第一和第二数据保持寄存器中，然后由每个数据保持寄存器输出大于时钟信号周期的时间。 输入数据值要被写入的地址值交替存储在第一和第二地址保持寄存器中。 存储在第一数据保持寄存器中的数据被写入由存储在第一地址保持寄存器中的地址值指示的第一存储体中的基于锁存器的存储元件。 存储在第二数据保持寄存器中的数据被写入由存储在第二地址保持寄存器中的地址值指示的第二存储体中的基于锁存器的存储元件。