公开(公告)号：US4920285A

公开(公告)日：1990-04-24

申请号：US274167

申请日：1988-11-21

申请人： Edward T. Clark ,  Enrique Ferrer

发明人： Edward T. Clark ,  Enrique Ferrer

IPC分类号： H03K17/00 ,  H03K17/081 ,  H03K17/691 ,  H03K17/693 ,  H04B1/18 ,  H04B1/40

CPC分类号： H03K17/691 ,  H03K17/08104 ,  H03K17/693 ,  Y10T307/74

摘要： An RF signal is transformed (12 and 12') to increase its current component, while reducing its voltage component below the voltage that would damage a GaAs switching device (16 or 16'). The current and voltage transformation are selected so that the power of the RF signal remains substantially constant. Subsequent to the GaAs switching device, the signal is converted (24 and 24') to increase the voltage component while decreasing its current component to substantially recreate the original RF signal.

摘要翻译： RF信号被变换（12和12'）以增加其电流分量，同时将其电压分量降低到低于将损坏GaAs开关器件（16或16'）的电压。 选择电流和电压变换使得RF信号的功率保持基本恒定。 在GaAs开关器件之后，信号被转换（24和24'）以增加电压分量，同时降低其电流分量，从而基本上重现原始RF信号。

公开(公告)号：US6160859A

公开(公告)日：2000-12-12

申请号：US174628

申请日：1998-10-19

申请人： William J. Martin ,  William J. Turney ,  Paul H. Gailus ,  Edward T. Clark ,  Joshua E. Dorevitch ,  Terry K. Mansfield

发明人： William J. Martin ,  William J. Turney ,  Paul H. Gailus ,  Edward T. Clark ,  Joshua E. Dorevitch ,  Terry K. Mansfield

IPC分类号： H04B1/00 ,  H04B1/28 ,  H04L27/08

CPC分类号： H04B1/005 ,  H04B1/00 ,  H04B1/28

摘要： An integrated multi-mode bandpass sigma-delta radio frequency receiver subsystem with interference mitigation includes a first intermediate frequency amplifier. At least one mixer for mixing the output of the first amplifier and an oscillator signal. A second IF amplifier for amplifying and filtering the output of the at least one mixer. A multi mode multi bandwidth sigma delta analog digital converter for providing digital output signals with high dynamic range. A digital mixer providing I and Q signals a decimation network providing I and Q signals at reduced programmable data and clock frequencies and a formatting network for arranging the I and Q signals into a predetermined format for use with a digital signal processor.

摘要翻译： 具有干扰抑制的集成多模式带通Σ-Δ射频接收器子系统包括第一中频放大器。 用于混合第一放大器的输出和振荡器信号的至少一个混频器。 用于放大和滤波至少一个混频器的输出的第二IF放大器。 一种多模式多带宽Σ-Δ模拟数字转换器，用于提供高动态范围的数字输出信号。 提供I和Q的数字混合器发信号通过减少的可编程数据和时钟频率提供I和Q信号的抽取网络和用于将I和Q信号布置成用于数字信号处理器的预定格式的格式化网络。

公开(公告)号：US06356603B1

公开(公告)日：2002-03-12

申请号：US09642491

申请日：2000-08-18

申请人： William J. Martin ,  William J. Turney ,  Paul H. Gailus ,  Edward T. Clark ,  Joshua E. Dorevitch ,  Terry K. Mansfield

发明人： William J. Martin ,  William J. Turney ,  Paul H. Gailus ,  Edward T. Clark ,  Joshua E. Dorevitch ,  Terry K. Mansfield

IPC分类号： H04L2708

CPC分类号： H04B1/005 ,  H04B1/00 ,  H04B1/28

摘要： An integrated sigma-delta radio frequency (RF) receiver subsystem (200) and method utilizes a multi-mode sigma-delta analog-to-digital converter (215) for providing a single and multi-bit output. A programmable decimation network (221) for reducing the frequency of the in-phase and quadrature bit stream and a programmable formatting network (223) are also used for organizing the in-phase and quadrature components from the decimation network (221) for subsequent signal processing. The invention offers a highly integrated digital/analog RF receiver back-end which incorporates integrated filtering and a smart gain control that is compatible for use with other receiver systems and offering superior performance characteristics.

摘要翻译： 集成的Σ-Δ射频（RF）接收机子系统（200）和方法利用多模式Σ-Δ模数转换器（215）来提供单位和多位输出。 用于降低同相和正交比特流的频率的可编程抽取网络（221）和可编程格式化网络（223）也用于从抽取网络（221）组织用于后续信号的同相和正交分量 处理。 本发明提供高度集成的数字/模拟RF接收机后端，其包括集成滤波和智能增益控制，其与其他接收机系统兼容并且提供优异的性能特性。

公开(公告)号：US5047674A

公开(公告)日：1991-09-10

申请号：US517899

申请日：1990-05-02

申请人： Edward T. Clark ,  Enrique Ferrer

发明人： Edward T. Clark ,  Enrique Ferrer

IPC分类号： H01Q1/52 ,  H01Q3/24

CPC分类号： H01Q1/525 ,  H01Q3/24 ,  Y10T307/74

摘要： A voltage multiplier rectifier filter circuit comprising capacitors C3 and C4 and diodes D1 and D3 multiples, rectifies and filters the voltage at an input terminal (T1) of the switch. A diode (D2) is connected to the output of the multiplier-rectifier-filter circuit to provide a lesser bias voltage in the absence of a signal at the input terminal (T1). Four transistors (Q1-Q4) switch this bias voltage ON and OFF to the gates of four GaAs transistors (S1-S4). The GaAs transistors selectively couple signals between the input and output signal terminals (T1-T4) of the switch.

摘要翻译： 包括电容器C3和C4以及二极管D1和D3的倍压整流滤波器电路对开关的输入端（T1）的电压进行倍数整流和滤波。 二极管（D2）连接到乘法器整流滤波电路的输出，以在输入端（T1）处不存在信号时提供较小的偏置电压。 四个晶体管（Q1-Q4）将该偏压电压切换为四个GaAs晶体管（S1-S4）的栅极。 GaAs晶体管选择性地耦合开关的输入和输出信号端子（T1-T4）之间的信号。

公开(公告)号：US4987392A

公开(公告)日：1991-01-22

申请号：US258934

申请日：1988-10-17

申请人： Edward T. Clark ,  Enrique Ferrer

发明人： Edward T. Clark ,  Enrique Ferrer

IPC分类号： H01P1/15

CPC分类号： H01P1/15

摘要： An electronic switch uses GaAs transistors to switch signals that have peak-to-peak voltage swings that exceed the breakdown voltage of the transistors. A two port impedance transformer (Z1) has a high input impedance and a low output impedance to transform a high voltage input signal (at T1) to a corresponding output signal having lower voltage, but higher current. This transformed signal is coupled to the second port of a three port impedance transformer (Z2) through a first GaAs transistor switch (Q1). A half wave rectifier circuit (D1, R7, R8 and C3) generates a negative DC voltage from the input signal (at T1), thereby eliminating the requirement for a separate bias voltage supply. A bipolar transistor switch selectively couples this negative bias voltage to the gate of the first GaAs transistor (Q1). The second port of the three port impedance transformer (Z2) has a lower impedance than either the first or third ports. A second GaAs transistor switch (Q2) is coupled between the third port of the three port impedance transformer (Z2) and ground, and a third GaAs transistor switch (Q3) couples the third port to a output terminal (T6) of the switch. The first port of the three port impedance transformer (Z2) is coupled to an input/output terminal (T2) of the switch.

摘要翻译： 电子开关使用GaAs晶体管来切换具有超过晶体管的击穿电压的峰 - 峰电压摆幅的信号。 双端口阻抗变压器（Z1）具有高输入阻抗和低输出阻抗，以将高电压输入信号（T1）转换为具有较低电压但较高电流的相应输出信号。 该变换信号通过第一GaAs晶体管开关（Q1）耦合到三端口阻抗变压器（Z2）的第二端口。 半波整流电路（D1，R7，R8和C3）从输入信号（T1）产生负直流电压，从而消除了对单独偏置电压供电的要求。 双极晶体管开关将该负偏置电压选择性地耦合到第一GaAs晶体管（Q1）的栅极。 三端口阻抗变压器（Z2）的第二个端口的阻抗比第一或第三端口低。 第二GaAs晶体管开关（Q2）耦合在三端口阻抗变压器（Z2）的第三端口和地之间，第三GaAs晶体管开关（Q3）将第三端口耦合到开关的输出端子（T6）。 三端口阻抗变压器（Z2）的第一端口耦合到开关的输入/输出端子（T2）。

公开(公告)号：US5001776A

公开(公告)日：1991-03-19

申请号：US263146

申请日：1988-10-27

申请人： Edward T. Clark

发明人： Edward T. Clark

IPC分类号： H04B1/10

CPC分类号： H04B1/109

摘要： A transceiver determines the signal quality of a desired signal and the strength of all received signals. When the signal quality of the desired signal is low, and the signal strength of all received signals is high, the receiver is adapted to operate in a higher current mode, thereby minimizing intermodulation distortion. Conversely, when the quality of the desired signal is low and the strength of all received signals is also low, or when the quality of the desired signal is above a threshold, the receiver operates in a lower current mode to conserve power and maximize battery lifetime. Also, when the transceiver adapts to operate in the higher current mode, a command is sent instructing a transmitting party to increase the quality of their message which may enable the listening transceiver to adapt (return) to a lower current mode.