公开(公告)号：US06727126B2

公开(公告)日：2004-04-27

申请号：US10335325

申请日：2002-12-30

申请人： Makoto Inai ,  Eiji Tai ,  Hidehiko Sasaki

发明人： Makoto Inai ,  Eiji Tai ,  Hidehiko Sasaki

IPC分类号： H01L21338

CPC分类号： H01L21/28587 ,  H01L21/0272

摘要： A fine electrode-forming masking member for forming fine gate electrodes, which can decrease gate length of a gate electrode of a field effect transistor. The method includes forming a first masking member having penetrating portions formed into opening patterns in conformity with the fine gate electrodes, on a semiconductor substrate using a photosensitive resin; and heating the first masking member so that parts of sidewalk in contact with the substrate of the penetrating portions flow along the semiconductor substrate to form extension portions. Accordingly, the widths of the penetrating portions at the bottom surface side are decreased so as to form the opening patterns. Gate electrodes are formed on regions of the semiconductor substrate exposed through the opening patterns while the substrate is masked with the fine electrode-forming masking member.

摘要翻译： 一种用于形成精细栅极的精细电极形成掩模构件，其可以减小场效应晶体管的栅电极的栅极长度。 该方法包括在使用感光树脂的半导体衬底上形成具有形成为与精细栅电极一致的开口图案的穿透部分的第一掩模构件; 并且加热第一遮蔽部件，使得与穿透部的基板接触的人行道的一部分沿着半导体基板流动，形成延伸部。 因此，底面侧的贯通部的宽度减小，形成开口图形。 在通过开口图案曝光的半导体衬底的区域上形成栅电极，同时用细电极形成掩模构件掩蔽衬底。

公开(公告)号：US06835635B2

公开(公告)日：2004-12-28

申请号：US10316210

申请日：2002-12-10

申请人： Hiroyuki Seto ,  Makoto Inai ,  Hiroyuki Nakano ,  Eiji Tai

发明人： Hiroyuki Seto ,  Makoto Inai ,  Hiroyuki Nakano ,  Eiji Tai

IPC分类号： H01L2128

CPC分类号： H01L29/66863 ,  H01L21/0272 ,  H01L21/28587

摘要： A gate electrode is formed in the following manner. A first resist layer having a first opening is formed on a semiconductor substrate. A second resist layer having a second opening larger than the first opening is formed on the first resist layer. A first conductor layer containing a high-melting-point metal is formed. Subsequently, a second conductor layer containing low-resistance metal is formed, and then the first conductor layer within the second opening is removed by etching. Next, the second resist layer is removed by a lift-off process, and finally the first resist layer is removed by ashing.

摘要翻译： 以下列方式形成栅电极。 在半导体衬底上形成具有第一开口的第一抗蚀剂层。 在第一抗蚀剂层上形成具有大于第一开口的第二开口的第二抗蚀剂层。 形成含有高熔点金属的第一导体层。 随后，形成含有低电阻金属的第二导体层，然后通过蚀刻去除第二开口内的第一导体层。 接下来，通过剥离处理去除第二抗蚀剂层，最后通过灰化除去第一抗蚀剂层。