公开(公告)号：US06526549B1

公开(公告)日：2003-02-25

申请号：US09662387

申请日：2000-09-14

Applicant: Eileen H. You

Inventor： Eileen H. You

IPC: G06F945

CPC classification number: G06F17/5036

Abstract: A method for extracting parasitic capacitance from an integrated circuit layout includes decomposing nets in the integrated circuit layout into conductive segments along two mutually perpendicular directions. The method further includes summing capacitances between the conductive segments in a selected net and the other conductive segments in the integrated circuit layout that are aligned with the conductive segments in the selected net and multiplying the sum by a first scaling factor to obtain a first capacitance value. The method further includes summing capacitances between the conductive segments in the selected net and the other conductive segments in the integrated circuit layout that are transverse to the conductive segments in the selected net to obtain a second capacitance value. The first capacitance value and the second capacitance value are added together to obtain a total capacitance value for the selected net.

Abstract translation: 从集成电路布局提取寄生电容的方法包括：将集成电路布局中的网络沿两个相互垂直的方向分解成导电段。 该方法进一步包括将所选择的网络中的导电段和集成电路布局中的其它导电段之间的电容相加，与所选网络中的导电段对准，并将和乘以第一缩放因子以获得第一电容值 。 该方法进一步包括将集成电路布局中的所选网络中的导电段与横向于所选网络中的导电段的其它导电段之间的导电段之间的电容相加以获得第二电容值。 将第一电容值和第二电容值相加，以获得所选网络的总电容值。

公开(公告)号：US06799308B2

公开(公告)日：2004-09-28

申请号：US10325806

申请日：2002-12-19

Applicant: Eileen H. You ,  Matthew E. Becker ,  Thomas E. Dillinger ,  Micah C. Knapp ,  Daniel J. Flees ,  Peter R. O'Brien ,  Chung Lau Chan

Inventor： Eileen H. You ,  Matthew E. Becker ,  Thomas E. Dillinger ,  Micah C. Knapp ,  Daniel J. Flees ,  Peter R. O'Brien ,  Chung Lau Chan

IPC: G06F1750

CPC classification number: G06F17/5031

Abstract: In accordance with the present invention, a method, system, computer system, and computer program product for considering clock skew in designing digital systems with latch-controlled circuits are provided. The disclosure teaches a method for determining whether logic operations can be performed within the available time and allows detailed modeling of clock skew for different domains of the integrated circuit. Taking clock skew into account for each domain, worst-case timing paths can be determined for circuits controlled by either flip-flops or latches. A design of an integrated circuit can be revised or verified using the method taught. The disclosure envisions that integrated circuits, printed circuit boards, computer systems and other components will be manufactured based upon designs developed with the method taught.

公开(公告)号：US06449754B1

公开(公告)日：2002-09-10

申请号：US09534280

申请日：2000-03-24

Applicant: Eileen H. You ,  Weize Xie ,  John F. MacDonald

Inventor： Eileen H. You ,  Weize Xie ,  John F. MacDonald

IPC: G06F1750

CPC classification number: G06F17/5036

Abstract: A technique measuring accuracy of parasitic capacitance extraction defines the error in an extracted total net parasitic capacitance intended for timing analysis as a sum of the errors in the extracted values of the individual capacitance elements, with the error for each element being influenced by a weight factor. Similarly, the technique defines an error in the extracted value of a crosstalk factor for the net of interest as a difference between the errors in the extracted values of the individual capacitance elements, with the error in each element being influenced by a weight factor. For signal timing and crosstalk analyses, the weight factors allow a designer to focus calibration of the extraction tool on the capacitive element having the highest weight factor.

Abstract translation: 一种测量寄生电容提取精度的技术将提取的用于定时分析的总净寄生电容的误差定义为各个电容元件的提取值中的误差之和，每个元件的误差受体重因子的影响 。 类似地，该技术将提取的感兴趣的串扰因子的提取值中的误差定义为各个电容元件的提取值中的误差之间的差异，每个元素的误差受到权重因子的影响。 对于信号定时和串扰分析，权重因子允许设计师将提取工具的校准聚焦在具有最高权重因子的电容元件上。