Method of manufacturing an integrated circuit with MOS transistors
having high breakdown voltages, and with precision resistors
    1.
    发明授权
    Method of manufacturing an integrated circuit with MOS transistors having high breakdown voltages, and with precision resistors 失效
    制造具有高击穿电压的MOS晶体管的集成电路的方法,以及精密电阻器

    公开(公告)号:US6027965A

    公开(公告)日:2000-02-22

    申请号:US67126

    申请日:1998-04-27

    摘要: The method described provides for the formation of an implantation mask of polycrystalline silicon comprising strips for providing the gate electrodes of the MOS transistors and portions defining openings for the formation of resistors. The method further includes low-dose ionic implantation through the implantation mask to form pairs of regions at the sides of the gate strips and resistive regions through the openings, the formation of an insulating layer on the entire structure thus produced, and anisotropic etching of the insulating layer so as to uncover the areas of the substrate not covered by the polycrystalline silicon mask, but leaving a residue of insulating material along the edges of the gate strips. To compensate for the removal of a surface layer from the resistive regions due to the anisotropic etching, a second low-dose implantation is carried out without masking of the substrate, with a dose and an energy such as to produce a predetermined resistivity for the resistive regions without altering the resistivities of the source and drain regions of the MOS transistors.

    摘要翻译: 所描述的方法提供了形成多晶硅的注入掩模,其包括用于提供MOS晶体管的栅电极和限定用于形成电阻器的开口的部分的条。 该方法还包括通过注入掩模的低剂量离子注入,以通过开口在栅极条和电阻区的侧面上形成一对区域,在由此产生的整个结构上形成绝缘层,以及各向异性蚀刻 绝缘层以露出未被多晶硅掩模覆盖的衬底的区域,但沿栅极条的边缘留下绝缘材料残留物。 为了补偿由于各向异性蚀刻而从电阻区域去除表面层,进行第二次低剂量注入,而不用衬底掩蔽,具有剂量和能量,以产生用于电阻的预定电阻率 区,而不改变MOS晶体管的源区和漏区的电阻率。