公开(公告)号：US20120110392A1

公开(公告)日：2012-05-03

申请号：US13345260

申请日：2012-01-06

申请人： Tse-Yu Yeh ,  Po-Yung Chang ,  Eric Hao

发明人： Tse-Yu Yeh ,  Po-Yung Chang ,  Eric Hao

IPC分类号： G06F11/30

CPC分类号： G06F9/3824 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/3832 ,  G06F9/3861

摘要： In one embodiment, a processor comprises a circuit coupled to receive an indication of a memory operation to be executed in the processor. The circuit is configured to predict whether or not the memory operation is misaligned. A number of accesses performed by the processor to execute the memory operation is dependent on whether or not the circuit predicts the memory operation as misaligned. In another embodiment, a misalignment predictor is coupled to receive an indication of a memory operation, and comprises a memory and a control circuit coupled to the memory. The memory is configured to store a plurality of indications of memory operations previously detected as misaligned during execution in a processor. The control circuit is configured to predict whether or not a memory operation is misaligned responsive to a comparison of the received indication and the plurality of indications stored in the memory.

摘要翻译： 在一个实施例中，处理器包括耦合以接收要在处理器中执行的存储器操作的指示的电路。 电路被配置为预测存储器操作是否不对准。 由处理器执行的执行存储器操作的多个访问取决于电路是否将存储器操作预测为未对准。 在另一个实施例中，未对准预测器被耦合以接收存储器操作的指示，并且包括耦合到存储器的存储器和控制电路。 存储器被配置为存储先前在处理器中执行期间被检测为未对准的存储器操作的多个指示。 控制电路被配置为响应于所接收的指示与存储在存储器中的多个指示的比较来预测存储器操作是否失准。

公开(公告)号：US07984274B2

公开(公告)日：2011-07-19

申请号：US12486917

申请日：2009-06-18

申请人： Sudarshan Kadambi ,  Po-Yung Chang ,  Eric Hao

发明人： Sudarshan Kadambi ,  Po-Yung Chang ,  Eric Hao

IPC分类号： G06F9/00

CPC分类号： G06F9/3834 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/3826 ,  G06F9/3838

摘要： In one embodiment, a processor comprises a prediction circuit and another circuit coupled to the prediction circuit. The prediction circuit is configured to predict whether or not a first load instruction will experience a partial store to load forward (PSTLF) event during execution. A PSTLF event occurs if a plurality of bytes, accessed responsive to the first load instruction during execution, include at least a first byte updated responsive to a previous uncommitted store operation and also include at least a second byte not updated responsive to the previous uncommitted store operation. Coupled to receive the first load instruction, the circuit is configured to generate one or more load operations responsive to the first load instruction. The load operations are to be executed in the processor to execute the first load instruction, and a number of the load operations is dependent on the prediction by the prediction circuit.

摘要翻译： 在一个实施例中，处理器包括预测电路和耦合到预测电路的另一电路。 预测电路被配置为预测在执行期间第一加载指令是否将经历部分存储以进行加载（PSTLF）事件。 如果响应于执行期间的第一加载指令访问的多个字节包括至少响应于先前未提交的存储操作而更新的第一字节，并且还包括响应于先前未提交的存储器而不更新的至少第二字节，则发生PSTLF事件 操作。 耦合以接收第一加载指令，该电路被配置为响应于第一加载指令生成一个或多个加载操作。 在处理器中执行加载操作以执行第一加载指令，并且多个加载操作取决于预测电路的预测。

公开(公告)号：US08549266B2

公开(公告)日：2013-10-01

申请号：US13155291

申请日：2011-06-07

申请人： John P. Banning ,  Eric Hao ,  Brett Coon

发明人： John P. Banning ,  Eric Hao ,  Brett Coon

IPC分类号： G06F9/30

CPC分类号： G06F9/3017

摘要： A method and system of instruction modification. A first machine language instruction, which may comprise a plurality of discrete instructions, is fetched. Responsive to a trigger pattern in the first machine language instruction, a segment of the first machine language instruction is modified. Information can be substituted into the segment based on specifics outlined in the trigger pattern. Alternatively, information can be combined with the segment via logical and/or arithmetic operations. Modification of the segment produces a second machine language instruction that is executed by units of the processor. In one embodiment, information may be taken from a queue and used to replace data from the segment. How information is taken from the queue and how the information so taken is used to replace fields of the segment are defined by the trigger pattern.

摘要翻译： 可以获取可以包括多个离散指令的第一机器语言指令。 响应于第一机器语言指令中的触发模式，第一机器语言指令的段被修改。 信息可以根据触发模式中概述的细节代替到细分。 或者，可以通过逻辑和/或算术运算将信息与段组合。 段的修改产生由处理器的单元执行的第二机器语言指令。 在一个实施例中，可以从队列中获取信息，并用于替换来自段的数据。 如何从队列中获取信息，以及如何使用如此使用的信息来替换段的字段由触发模式定义。

公开(公告)号：US07568087B2

公开(公告)日：2009-07-28

申请号：US12055016

申请日：2008-03-25

申请人： Sudarshan Kadambi ,  Po-Yung Chang ,  Eric Hao

发明人： Sudarshan Kadambi ,  Po-Yung Chang ,  Eric Hao

IPC分类号： G06F7/38 ,  G06F9/00

CPC分类号： G06F9/3834 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/3826 ,  G06F9/3838

摘要： In one embodiment, a processor comprises a prediction circuit and another circuit coupled to the prediction circuit. The prediction circuit is configured to predict whether or not a first load instruction will experience a partial store to load forward (PSTLF) event during execution. A PSTLF event occurs if a plurality of bytes, accessed responsive to the first load instruction during execution, include at least a first byte updated responsive to a previous uncommitted store operation and also include at least a second byte not updated responsive to the previous uncommitted store operation. Coupled to receive the first load instruction, the circuit is configured to generate one or more load operations responsive to the first load instruction. The load operations are to be executed in the processor to execute the first load instruction, and a number of the load operations is dependent on the prediction by the prediction circuit.

摘要翻译： 在一个实施例中，处理器包括预测电路和耦合到预测电路的另一电路。 预测电路被配置为预测在执行期间第一加载指令是否将经历部分存储以进行加载（PSTLF）事件。 如果响应于执行期间的第一加载指令访问的多个字节包括至少响应于先前未提交的存储操作而更新的第一字节，并且还包括响应于先前未提交的存储器而不更新的至少第二字节，则发生PSTLF事件 操作。 耦合以接收第一加载指令，该电路被配置为响应于第一加载指令生成一个或多个加载操作。 在处理器中执行加载操作以执行第一加载指令，并且多个加载操作取决于预测电路的预测。

公开(公告)号：US20080177988A1

公开(公告)日：2008-07-24

申请号：US12055016

申请日：2008-03-25

申请人： Sudarshan Kadambi ,  Po-Yung Chang ,  Eric Hao

发明人： Sudarshan Kadambi ,  Po-Yung Chang ,  Eric Hao

IPC分类号： G06F9/312

CPC分类号： G06F9/3834 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/3826 ,  G06F9/3838

摘要： In one embodiment, a processor comprises a prediction circuit and another circuit coupled to the prediction circuit. The prediction circuit is configured to predict whether or not a first load instruction will experience a partial store to load forward (PSTLF) event during execution. A PSTLF event occurs if a plurality of bytes, accessed responsive to the first load instruction during execution, include at least a first byte updated responsive to a previous uncommitted store operation and also include at least a second byte not updated responsive to the previous uncommitted store operation. Coupled to receive the first load instruction, the circuit is configured to generate one or more load operations responsive to the first load instruction. The load operations are to be executed in the processor to execute the first load instruction, and a number of the load operations is dependent on the prediction by the prediction circuit.

摘要翻译： 在一个实施例中，处理器包括预测电路和耦合到预测电路的另一电路。 预测电路被配置为预测在执行期间第一加载指令是否将经历部分存储以进行加载（PSTLF）事件。 如果响应于执行期间的第一加载指令访问的多个字节包括至少响应于先前未提交的存储操作而更新的第一字节，并且还包括响应于先前未提交的存储器而不更新的至少第二字节，则发生PSTLF事件 操作。 耦合以接收第一加载指令，该电路被配置为响应于第一加载指令生成一个或多个加载操作。 在处理器中执行加载操作以执行第一加载指令，并且多个加载操作取决于预测电路的预测。

公开(公告)号：US07376817B2

公开(公告)日：2008-05-20

申请号：US11200744

申请日：2005-08-10

申请人： Sudarshan Kadambi ,  Po-Yung Chang ,  Eric Hao

发明人： Sudarshan Kadambi ,  Po-Yung Chang ,  Eric Hao

IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44

CPC分类号： G06F9/3834 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/3826 ,  G06F9/3838

摘要： In one embodiment, a processor comprises a prediction circuit and another circuit coupled to the prediction circuit. The prediction circuit is configured to predict whether or not a first load instruction will experience a partial store to load forward (PSTLF) event during execution. A PSTLF event occurs if a plurality of bytes, accessed responsive to the first load instruction during execution, include at least a first byte updated responsive to a previous uncommitted store operation and also include at least a second byte not updated responsive to the previous uncommitted store operation. Coupled to receive the first load instruction, the circuit is configured to generate one or more load operations responsive to the first load instruction. The load operations are to be executed in the processor to execute the first load instruction, and a number of the load operations is dependent on the prediction by the prediction circuit.

摘要翻译： 在一个实施例中，处理器包括预测电路和耦合到预测电路的另一电路。 预测电路被配置为预测在执行期间第一加载指令是否将经历部分存储以进行加载（PSTLF）事件。 如果响应于执行期间的第一加载指令访问的多个字节包括至少响应于先前未提交的存储操作而更新的第一字节，并且还包括响应于先前未提交的存储器而不更新的至少第二字节，则发生PSTLF事件 操作。 耦合以接收第一加载指令，该电路被配置为响应于第一加载指令生成一个或多个加载操作。 在处理器中执行加载操作以执行第一加载指令，并且多个加载操作取决于预测电路的预测。

公开(公告)号：US08171240B1

公开(公告)日：2012-05-01

申请号：US13345260

申请日：2012-01-06

申请人： Tse-Yu Yeh ,  Po-Yung Chang ,  Eric Hao

发明人： Tse-Yu Yeh ,  Po-Yung Chang ,  Eric Hao

IPC分类号： G06F12/00

CPC分类号： G06F9/3824 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/3832 ,  G06F9/3861

摘要： In one embodiment, a processor comprises a circuit coupled to receive an indication of a memory operation to be executed in the processor. The circuit is configured to predict whether or not the memory operation is misaligned. A number of accesses performed by the processor to execute the memory operation is dependent on whether or not the circuit predicts the memory operation as misaligned. In another embodiment, a misalignment predictor is coupled to receive an indication of a memory operation, and comprises a memory and a control circuit coupled to the memory. The memory is configured to store a plurality of indications of memory operations previously detected as misaligned during execution in a processor. The control circuit is configured to predict whether or not a memory operation is misaligned responsive to a comparison of the received indication and the plurality of indications stored in the memory.

公开(公告)号：US20110238961A1

公开(公告)日：2011-09-29

申请号：US13155291

申请日：2011-06-07

申请人： John Banning ,  Eric Hao ,  Brett Coon

发明人： John Banning ,  Eric Hao ,  Brett Coon

IPC分类号： G06F9/30

CPC分类号： G06F9/3017

摘要： A method and system of instruction modification. A first machine language instruction, which may comprise a plurality of discrete instructions, is fetched. Responsive to a trigger pattern in the first machine language instruction, a segment of the first machine language instruction is modified. Information can be substituted into the segment based on specifics outlined in the trigger pattern. Alternatively, information can be combined with the segment via logical and/or arithmetic operations. Modification of the segment produces a second machine language instruction that is executed by units of the processor. In one embodiment, information may be taken from a queue and used to replace data from the segment. How information is taken from the queue and how the information so taken is used to replace fields of the segment are defined by the trigger pattern.

摘要翻译： 指令修改的方法和系统。 可以获取可以包括多个离散指令的第一机器语言指令。 响应于第一机器语言指令中的触发模式，第一机器语言指令的段被修改。 信息可以根据触发模式中概述的细节代替到细分。 或者，可以通过逻辑和/或算术运算将信息与段组合。 段的修改产生由处理器的单元执行的第二机器语言指令。 在一个实施例中，可以从队列中获取信息，并用于替换来自段的数据。 如何从队列中获取信息，以及如何使用如此使用的信息来替换段的字段由触发模式定义。

公开(公告)号：US07984277B2

公开(公告)日：2011-07-19

申请号：US12698809

申请日：2010-02-02

申请人： John Banning ,  Eric Hao ,  Brett Coon

发明人： John Banning ,  Eric Hao ,  Brett Coon

IPC分类号： G06F9/30

CPC分类号： G06F9/3017

摘要： A method and system of instruction modification. A first machine language instruction, which may comprise a plurality of discrete instructions, is fetched. Responsive to a trigger pattern in the first machine language instruction, a segment of the first machine language instruction is modified. Information can be substituted into the segment based on specifics outlined in the trigger pattern. Alternatively, information can be combined with the segment via logical and/or arithmetic operations. Modification of the segment produces a second machine language instruction that is executed by units of the processor. In one embodiment, information may be taken from a queue and used to replace data from the segment. How information is taken from the queue and how the information so taken is used to replace fields of the segment are defined by the trigger pattern.

摘要翻译： 指令修改的方法和系统。 可以获取可以包括多个离散指令的第一机器语言指令。 响应于第一机器语言指令中的触发模式，第一机器语言指令的段被修改。 信息可以根据触发模式中概述的细节代替到细分。 或者，可以通过逻辑和/或算术运算将信息与段组合。 段的修改产生由处理器的单元执行的第二机器语言指令。 在一个实施例中，可以从队列中获取信息，并用于替换来自段的数据。 如何从队列中获取信息，以及如何使用如此使用的信息来替换段的字段由触发模式定义。

公开(公告)号：US20070038847A1

公开(公告)日：2007-02-15

申请号：US11200771

申请日：2005-08-10

申请人： Tse-Yu Yeh ,  Po-Yung Chang ,  Eric Hao

发明人： Tse-Yu Yeh ,  Po-Yung Chang ,  Eric Hao

IPC分类号： G06F9/44

CPC分类号： G06F9/3824 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/3832 ,  G06F9/3861

摘要： In one embodiment, a processor comprises a circuit coupled to receive an indication of a memory operation to be executed in the processor. The circuit is configured to predict whether or not the memory operation is misaligned. A number of accesses performed by the processor to execute the memory operation is dependent on whether or not the circuit predicts the memory operation as misaligned. In another embodiment, a misalignment predictor is coupled to receive an indication of a memory operation, and comprises a memory and a control circuit coupled to the memory. The memory is configured to store a plurality of indications of memory operations previously detected as misaligned during execution in a processor. The control circuit is configured to predict whether or not a memory operation is misaligned responsive to a comparison of the received indication and the plurality of indications stored in the memory.

摘要翻译： 在一个实施例中，处理器包括耦合以接收要在处理器中执行的存储器操作的指示的电路。 电路被配置为预测存储器操作是否不对准。 由处理器执行的执行存储器操作的多个访问取决于电路是否将存储器操作预测为未对准。 在另一个实施例中，未对准预测器被耦合以接收存储器操作的指示，并且包括耦合到存储器的存储器和控制电路。 存储器被配置为存储先前在处理器中执行期间被检测为未对准的存储器操作的多个指示。 控制电路被配置为响应于所接收的指示与存储在存储器中的多个指示的比较来预测存储器操作是否失准。