Runtime optimizing applications for a target system from within a deployment server
    1.
    发明申请
    Runtime optimizing applications for a target system from within a deployment server 有权
    部署服务器内的目标系统的运行时优化应用程序

    公开(公告)号:US20060143601A1

    公开(公告)日:2006-06-29

    申请号:US11023855

    申请日:2004-12-28

    IPC分类号: G06F9/44

    CPC分类号: G06F8/64 G06F8/61

    摘要: A deployment server can include a profile data store, a generic application data store, and an optimizer. The profile data store can contain a plurality of attributes for devices and associate different optimization parameters or optimization routines to each of the stored attributes. The generic application data store can contain at least one generic application written in a device independent fashion. The optimizer can receive application requests from an assortment of different requesting devices and can dynamically generate device-specific applications responsive to received requests. For each requesting device, the optimizer can determine attributes of a requesting device, utilize the profile data store to identify optimization parameters or optimization routines for the requesting device, and generate a device-specific application based upon data from the profile data store and based upon a generic application retrieved from the generic application data store.

    摘要翻译: 部署服务器可以包括配置文件数据存储,通用应用数据存储和优化器。 简档数据存储可以包含用于设备的多个属性,并将不同的优化参数或优化例程关联到每个存储的属性。 通用应用程序数据存储可以包含以设备独立方式编写的至少一个通用应用程序。 优化器可以从各种不同的请求设备接收应用请求,并且可以响应于接收到的请求而动态生成针对设备的应用。 对于每个请求设备,优化器可以确定请求设备的属性,利用简档数据存储来识别请求设备的优化参数或优化例程,并且基于来自简档数据存储器的数据并基于 从通用应用程序数据存储检索的通用应用程序。

    Error checking and correcting for read-modified-write operations
    2.
    发明授权
    Error checking and correcting for read-modified-write operations 失效
    错误检查和更正读取 - 修改 - 写入操作

    公开(公告)号:US4884271A

    公开(公告)日:1989-11-28

    申请号:US138429

    申请日:1987-12-28

    IPC分类号: G06F12/16 G06F11/10

    CPC分类号: G06F11/1056

    摘要: Error detection and correction logic is interposed between a 16-bit CPU and a data storage unit with a 32-bit word size and single bit error correction and double bit error detection (ECC) code bits. During each CPU Read cycle, a full word and its ECC bits are read from storage; and a selected 16 data bits are transferred to the CPU directly if they are error free or are corrected by the ECC logic and then transferred if they have only one bit with an error. During each CPU Write cycle, a selected full word and its ECC bits are read from storage; 16 data bits of the word are replaced by 16 data bits from the CPU; ECC bits are calculated for the modified word; and the modified word and its ECC bits are entered into the storage unit so long as no error exists in the remaining 16 bits of the data word which were not replaced/modified. This type of operation is often referred to as a Read-Modify-Write (RMW) cycle. During this RMW operation, the ECC logic detects and corrects a single bit error (if one exists) concurrent with modification of the word and calculation of new ECC bits. The corrected word is then modified by the data bits from the CPU, new ECC bits are calculated and the latter modified word and ECC bits are entered into the storage unit rather than the former word which contained a single bit error. If no error exists, a short RMW cycle is used; if a single bit error exists a longer RMW cycle is used.

    Dynamically optimizing applications within a deployment server
    3.
    发明授权
    Dynamically optimizing applications within a deployment server 有权
    动态优化部署服务器中的应用程序

    公开(公告)号:US09535679B2

    公开(公告)日:2017-01-03

    申请号:US11023855

    申请日:2004-12-28

    IPC分类号: G06F9/45 G06F9/445

    CPC分类号: G06F8/64 G06F8/61

    摘要: A deployment server can include a profile data store, a generic application data store, and an optimizer. The profile data store can contain a plurality of attributes for devices and associate different optimization parameters or optimization routines to each of the stored attributes. The generic application data store can contain at least one generic application written in a device independent fashion. The optimizer can receive application requests from an assortment of different requesting devices and can dynamically generate device-specific applications responsive to received requests. For each requesting device, the optimizer can determine attributes of a requesting device, utilize the profile data store to identify optimization parameters or optimization routines for the requesting device, and generate a device-specific application based upon data from the profile data store and based upon a generic application retrieved from the generic application data store.

    摘要翻译: 部署服务器可以包括配置文件数据存储,通用应用数据存储和优化器。 简档数据存储可以包含用于设备的多个属性,并将不同的优化参数或优化例程关联到每个存储的属性。 通用应用程序数据存储可以包含以设备独立方式编写的至少一个通用应用程序。 优化器可以从各种不同的请求设备接收应用请求,并且可以响应于接收到的请求而动态生成针对设备的应用。 对于每个请求设备,优化器可以确定请求设备的属性,利用简档数据存储来识别请求设备的优化参数或优化例程,并且基于来自简档数据存储器的数据并基于 从通用应用程序数据存储检索的通用应用程序。

    PLA microcode controller
    4.
    发明授权
    PLA microcode controller 失效
    PLA微码控制器

    公开(公告)号:US5043879A

    公开(公告)日:1991-08-27

    申请号:US296168

    申请日:1989-01-12

    IPC分类号: G06F9/22 G06F9/26

    CPC分类号: G06F9/223

    摘要: To provide for efficient use of computer microcodes, a firmware structure containing a mainline programmable logic array circuit and at least one subroutine programmable logic array circuit may be used. As the states of the mainline programmable logic array circuit are sequenced, the data bits representing the encode number field in its OR array are compared with the data bits representing the encode number field of the AND array of the subroutine programmable logic array circuit. If a match is made, the mainline programmable logic array circuit suspends its operation and sequencing of the subroutine programmable logic array circuit begins, in order to perform the function required. Upon completion of the function, control is automatically transferred from the subroutine programmable logic array circuit back to the mainline programmable logic array circuit, at the point where it was suspended. By nesting a plurality of subroutine programmable logic array circuits, a plurality of functions, many of which may be performed simultaneously, can take place.