公开(公告)号：US07730251B2

公开(公告)日：2010-06-01

申请号：US11296451

申请日：2005-12-08

申请人： François Jeanjean

发明人： François Jeanjean

IPC分类号： G06F13/00 ,  G06F13/10 ,  H05K7/10 ,  H03K19/00 ,  G06F13/14

CPC分类号： H05K7/1455

摘要： A support identification device comprising a support (BPA), e.g. a rack or backplane of a telecommunication system, and an identity receiver (PCB), e.g. a printed circuit board or card, coupled to an identity transmitter or connector of the support. The identity transmitter has several read pins (id1-id4=R1-R4) each at a logical level (0, 1) to indicate (identify) the type of support. The card (PCB) further has write terminals (W1, W2) coupled to dynamic terminals (D1, D2) of the support (BPA). These dynamic terminals are coupled to one or more of the read pins (id1-id4). The card is also provided with a program that sets the write terminals at a first logical level, reads a first logical level at each read pin (R1-R4), then sets the write terminals at a second logical level, reads a second logical level at each read pin, and determines from the difference between the first and the second read logical levels to which write terminal each read terminal is coupled, or not. This allows to obtain (2+w)n identifications with n read pins and w write pins, instead of 2n+w identifications with the same total number n+w of read or basic pins.

摘要翻译： 支撑识别装置，包括支撑件（BPA），例如 电信系统的机架或背板，以及身份接收器（PCB），例如， 印刷电路板或卡，其耦合到所述支架的标识发射器或连接器。 身份发送器具有多个读取引脚（id1-id4 = R1-R4），每个读取引脚（逻辑1（1，1））以指示（识别）支持类型。 卡（PCB）还具有耦合到支撑件（BPA）的动态端子（D1，D2）的写入端子（W1，W2）。 这些动态端子耦合到一个或多个读引脚（id1-id4）。 该卡还设置有将写入端子设置在第一逻辑电平的程序，在每个读取引脚（R1-R4）处读取第一逻辑电平，然后将写入端子设置在第二逻辑电平，读取第二逻辑电平 并且根据每个读取终端所耦合的写入终端的第一和第二读取逻辑电平之间的差确定。 这允许使用n个读取引脚和w个写入引脚获取（2 + w）n个标识，而不是2n + w个标识，读取或基本引脚的总数n + w相同。

公开(公告)号：US07227934B2

公开(公告)日：2007-06-05

申请号：US10252406

申请日：2002-09-24

申请人： François JeanJean ,  Frank Octaaf Van der Putten

发明人： François JeanJean ,  Frank Octaaf Van der Putten

IPC分类号： H04M11/00

CPC分类号： H04M11/06

摘要： Conventional modems coupled in parallel to a coupling need a sharing apparatus, which can be avoided by providing each modem with a detector for detecting upstream/downstream signals to be transceived by other modems coupled in parallel. The detector has a distinguisher for distinguishing upstream signals and downstream signals. An additional filter between the coupling and detector prevents the modem from interfering with the other modems coupled in parallel. The modem may have an active/passive state corresponding with a lower/higher impedance.

摘要翻译： 与耦合并联耦合的传统调制解调器需要共享装置，这可以通过为每个调制解调器提供检测器来避免，该检测器用于检测由并联耦合的其他调制解调器收发的上行/下行信号。 检测器具有区分上行信号和下行信号的识别器。 耦合和检测器之间的附加滤波器防止调制解调器干扰并联耦合的其他调制解调器。 调制解调器可能具有对应于较低/较高阻抗的主动/被动状态。

公开(公告)号：US06954119B2

公开(公告)日：2005-10-11

申请号：US10337781

申请日：2003-01-08

申请人： François Jeanjean ,  Geert Arthur Edith Van Wonterghem

发明人： François Jeanjean ,  Geert Arthur Edith Van Wonterghem

IPC分类号： H03H1/02 ,  H03H7/01 ,  H03H11/12 ,  H03H7/00

CPC分类号： H03H7/1766 ,  H03H7/06 ,  H03H7/427 ,  H03H2260/00

摘要： A passive filter arrangement and a method of providing such a filter is described. The frequency response of the filter arrangement is substantially the same as the frequency response of a first filter of an order having a first value, the frequency response of the first filter being representable by a first set of one or more poles and/or one or more zeros. Descriptions of a plurality of second filters are generated, each second filter having an order lower than the order of the first value, each second filter having a frequency response representable by a one or more poles and/or one or more zeros, the one or more poles and/or one or more zeros of each lower order filter being a subset of the first set. The lower order filters are cascaded.

摘要翻译： 描述了一种无源滤波器装置和提供这种滤波器的方法。 滤波器装置的频率响应基本上与具有第一值的次序的第一滤波器的频率响应基本相同，第一滤波器的频率响应可由第一组一个或多个极和/或一个或多个极表示， 更多零。 产生多个第二滤波器的描述，每个第二滤波器具有低于第一值的次序的顺序，每个第二滤波器具有可由一个或多个极和/或一个或多个零表示的频率响应， 每个低阶滤波器的多个极点和/或一个或多个零点是第一组的子集。 低阶滤波器级联。