公开(公告)号：US6150707A

公开(公告)日：2000-11-21

申请号：US226243

申请日：1999-01-07

申请人： Robert K. Cook ,  Craig R. Gruszecki ,  Mark A. Passaro ,  Frederick A. Scholl

发明人： Robert K. Cook ,  Craig R. Gruszecki ,  Mark A. Passaro ,  Frederick A. Scholl

IPC分类号： H01L21/02 ,  H01L21/768 ,  H07L29/41

CPC分类号： H01L28/40 ,  H01L21/76838

摘要： The present invention provides a method for fabricating a capacitor within a semiconductor device comprising the steps of forming openings in an oxide dielectric to reach a lower conductor layer which will serve as a lower conductor plate of the capacitor; depositing capacitor electrode material, such as tungsten to fill the openings to form a capacitor electrode and planarizing the filled openings using chemical/mechanical polish; depositing a selected oxide capacitor dielectric over the capacitor electrodes and patterning the capacitor dielectric with photoresist to leave dielectric covering the area of the capacitor electrodes; stripping away the photoresist; adding an upper conductor layer on top of the capacitor dielectric to serve as the top plate of the capacitor. The above steps may be repeated to form multiple layers of capacitors within the semiconductor device.

摘要翻译： 本发明提供了一种在半导体器件内制造电容器的方法，包括以下步骤：在氧化物电介质中形成开口以到达将用作电容器的下导体板的下导体层; 沉积诸如钨的电容器电极材料以填充开口以形成电容器电极，并使用化学/机械抛光对填充的开口进行平坦化; 在电容器电极上沉积选定的氧化物电容器电介质，并用光致抗蚀剂构图电容器电介质以留下覆盖电容器电极区域的电介质; 剥离光致抗蚀剂; 在电容器电介质的顶部添加上导体层以用作电容器的顶板。 可以重复上述步骤以在半导体器件内形成多层电容器。

公开(公告)号：US6001702A

公开(公告)日：1999-12-14

申请号：US14934

申请日：1998-01-28

申请人： Robert K. Cook ,  Craig R. Gruszecki ,  Mark A. Passaro ,  Frederick A. Scholl

发明人： Robert K. Cook ,  Craig R. Gruszecki ,  Mark A. Passaro ,  Frederick A. Scholl

IPC分类号： H01L21/02 ,  H01L21/20

CPC分类号： H01L28/40

摘要： The present invention provides a method for fabricating a capacitor within a semiconductor device comprising the steps of forming openings in an oxide dielectric to reach a lower conductor layer which will serve as a lower conductor plate of the capacitor; depositing capacitor electrode material, such as tungsten to fill the openings to form a capacitor electrode and planarizing the filled openings using chemical/mechanical polish; depositing a selected oxide capacitor dielectric over the capacitor electrodes and patterning the capacitor dielectric with photoresist to leave dielectric covering the area of the capacitor electrodes; stripping away the photoresist; adding an upper conductor layer on top of the capacitor dielectric to serve as the top plate of the capacitor. The above steps may be repeated to form multiple layers of capacitors within the semiconductor device.

摘要翻译： 本发明提供了一种在半导体器件内制造电容器的方法，包括以下步骤：在氧化物电介质中形成开口以到达将用作电容器的下导体板的下导体层; 沉积诸如钨的电容器电极材料以填充开口以形成电容器电极，并使用化学/机械抛光对填充的开口进行平坦化; 在电容器电极上沉积选定的氧化物电容器电介质，并用光致抗蚀剂构图电容器电介质以留下覆盖电容器电极区域的电介质; 剥离光致抗蚀剂; 在电容器电介质的顶部添加上导体层以用作电容器的顶板。 可以重复上述步骤以在半导体器件内形成多层电容器。

公开(公告)号：US07962302B2

公开(公告)日：2011-06-14

申请号：US12329868

申请日：2008-12-08

申请人： Robert Jeffrey Baseman ,  Susan G. Conti ,  William A. Muth ,  Michal Rosen-Zvi ,  Frederick A. Scholl

发明人： Robert Jeffrey Baseman ,  Susan G. Conti ,  William A. Muth ,  Michal Rosen-Zvi ,  Frederick A. Scholl

IPC分类号： G06F19/00

CPC分类号： H01L22/20 ,  H01L22/14 ,  H01L2924/0002 ,  H01L2924/00

摘要： Techniques for estimating a quality of one or more wafers are presented. One or more first wafers comprising one or more first dies are tested. A probability of wafer failure is determined in accordance with one or more first test measurements of the one or more first dies. A pass status and/or a fail status of one or more second wafers is inferred by testing a select one or more second dies of the one or more second wafers and evaluating one or more second test measurements of the select one or more second dies in accordance with the determined probability of wafer failure.

摘要翻译： 提出了用于估计一个或多个晶片的质量的技术。 测试包括一个或多个第一裸片的一个或多个第一晶片。 根据一个或多个第一模具的一个或多个第一测试测量值确定晶片故障的概率。 通过测试一个或多个第二晶片的选择的一个或多个第二管芯并且评估所选择的一个或多个第二管芯的一个或多个第二测试测量结果来推断一个或多个第二晶片的通过状态和/或失败状态 根据确定的晶圆故障概率。

公开(公告)号：US20100145646A1

公开(公告)日：2010-06-10

申请号：US12329868

申请日：2008-12-08

申请人： Robert Jeffrey Baseman ,  Susan G. Conti ,  William A. Muth ,  Michal Rosen-Zvi ,  Frederick A. Scholl

发明人： Robert Jeffrey Baseman ,  Susan G. Conti ,  William A. Muth ,  Michal Rosen-Zvi ,  Frederick A. Scholl

IPC分类号： G06F19/00

CPC分类号： H01L22/20 ,  H01L22/14 ,  H01L2924/0002 ,  H01L2924/00

摘要： Techniques for estimating a quality of one or more wafers are presented. One or more first wafers comprising one or more first dies are tested. A probability of wafer failure is determined in accordance with one or more first test measurements of the one or more first dies. A pass status and/or a fail status of one or more second wafers is inferred by testing a select one or more second dies of the one or more second wafers and evaluating one or more second test measurements of the select one or more second dies in accordance with the determined probability of wafer failure.

摘要翻译： 提出了用于估计一个或多个晶片的质量的技术。 测试包括一个或多个第一裸片的一个或多个第一晶片。 根据一个或多个第一模具的一个或多个第一测试测量值确定晶片故障的概率。 通过测试一个或多个第二晶片的选择的一个或多个第二管芯并且评估所选择的一个或多个第二管芯的一个或多个第二测试测量结果来推断一个或多个第二晶片的通过状态和/或失败状态 根据确定的晶圆故障概率。