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公开(公告)号：US4702745A
公开(公告)日：1987-10-27
申请号：US857944
申请日：1986-05-01
申请人： Takao Kamei , Fuminobu Ono , Keiichi Komai , Takeshi Wakabayashi , Takayuki Ogawa , Hideaki Ito , Kiyoshi Shirakawa
发明人： Takao Kamei , Fuminobu Ono , Keiichi Komai , Takeshi Wakabayashi , Takayuki Ogawa , Hideaki Ito , Kiyoshi Shirakawa
摘要： A high moisture porous organic solid is dewatered by the steps of (1) heating the high moisture porous organic solid in a fluid medium having an elevated temperature and a high pressure, thereby reducing the moisture of the solid, (2) starting to compress the porous structure of the solid by mechanical means, while maintaining the temperature and the pressure of the surrounding fluid medium the same as in the final stage of step (1), and (3) lowering the pressure of the surrounding fluid medium while maintaining the mechanical compression of the solid, whereby the quality of the porous solid, such as apparent density and calorific values of moist solid per weight as well as per volume are considerably improved.
摘要翻译： 通过以下步骤使高水分多孔有机固体脱水：（1）在具有升高的温度和高压的流体介质中加热高水分多孔有机固体，从而降低固体的水分，（2）开始压缩 通过机械方式固体的多孔结构，同时保持周围流体介质的温度和压力与步骤（1）的最后阶段相同，和（3）降低周围流体介质的压力同时保持机械 固体的压缩，从而显着提高了多孔固体的质量，例如每重量和每体积的湿固体的表观密度和发热量。
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公开(公告)号：US06639453B2
公开(公告)日：2003-10-28
申请号：US09794698
申请日：2001-02-26
申请人： Yoshikazu Nishimura , Fuminobu Ono
发明人： Yoshikazu Nishimura , Fuminobu Ono
IPC分类号： G05F110
CPC分类号： G05F3/205
摘要： An active bias circuit having a combined configuration of the Wilson and Widlar current source configurations is provided, which makes it possible to set the output bias voltage at approximately 0V even if a reference voltage applied to generate a reference current does not reach 0V. This circuit comprises cascode-connected first and second transistors, cascode-connected third and fourth transistors, and a diode with a specific forward voltage drop generated by a current flowing through the diode itself. The absolute value of the output bias voltage is decreased by the value of the forward voltage drop of the diode compared with the case where the diode is not provided. The diode is provided between the source/emitter of the third transistor and the drain/collector of the fourth transistor, or between the connection point of the third and fourth transistors and the output terminal, or the gates/bases of the first and third transistors.
摘要翻译： 提供了具有Wilson和Widlar电流源配置的组合配置的有源偏置电路，这使得即使施加用于产生参考电流的参考电压没有达到0V，也可以将输出偏置电压设置在大约0V。 该电路包括共源共栅连接的第一和第二晶体管，共源共栅的第三和第四晶体管，以及具有由流过二极管本身的电流产生的特定的正向压降的二极管。 与未设置二极管的情况相比，输出偏置电压的绝对值减小二极管正向压降的值。 二极管设置在第三晶体管的源极/发射极与第四晶体管的漏极/集电极之间，或第三和第四晶体管的连接点与输出端之间，或第一和第三晶体管的栅极/基极之间 。
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公开(公告)号：US06515538B2
公开(公告)日：2003-02-04
申请号：US09837730
申请日：2001-04-18
申请人： Fuminobu Ono , Yoshikazu Nishimura
发明人： Fuminobu Ono , Yoshikazu Nishimura
IPC分类号： G05F110
摘要： An active bias circuit having a combined configuration of the Wilson and Widlar current source configurations is provided, which makes it possible to set the output bias voltage at approximately zero (OV) even if a reference voltage applied to generate a reference current does not reach OV. This circuit comprises cascode-connected first and second transistors cascode-connected third and fourth transistors, and a resistor with a specific voltage drop generated by a current flowing through the same. The absolute value of the output bias voltage is decreased by the value of the voltage drop of the resistor compared with the case where the resistor is not provided. The resistor is provided between the gates/bases of the first and third transistors, or between the gate/base and source/emitter of the fourth transistor.
摘要翻译： 提供了具有Wilson和Widlar电流源配置的组合配置的主动偏置电路，这使得即使用于产生参考电流的参考电压没有达到OV，也可以将输出偏置电压设置在大约为零（0V） 。 该电路包括共源共栅连接的第一和第二晶体管共源共栅三极管和第四晶体管，以及具有由流过其的电流产生的特定电压降的电阻器。 与未设置电阻器的情况相比，输出偏置电压的绝对值减小电阻器的电压降值。 电阻器设置在第一和第三晶体管的栅极/基极之间，或第四晶体管的栅极/基极和源极/发射极之间。
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公开(公告)号：US6078020A
公开(公告)日：2000-06-20
申请号：US970146
申请日：1997-11-13
申请人： Fuminobu Ono
发明人： Fuminobu Ono
CPC分类号： B23K1/0004 , B23K2201/40
摘要： In semiconductor device manufacturing apparatus and method, in a joining process of a semiconductor pellet (2) and a package (1), the semiconductor pellet (2) is kept to a temperature equilibrium state under an actual use temperature condition while a low melting-point soldering member (3) is interposed between the semiconductor pellet (2) and the package (1), and the electrode pads (9) on the upper surface of the semiconductor pellet (2) and the electrode terminals (8) of the collet (5), which is electrically connected to the output terminal of a high voltage electric pulse source (4), are fitted and electrically connected to each other. Subsequently, a high voltage electric pulse is produced in the high voltage electric pulse source (4) and applied to the electrode pads (9) to melt the low melting-point soldering member (3), causing joining of the package (1) and the semiconductor pellet (2). The joining treatment can be performed under the actual use temperature condition of the semiconductor pellet (2), and thermal stress to the semiconductor pellet (2) is suppressed and the lifetime of the semiconductor pellet (2) can be increased.
摘要翻译： 在半导体器件制造装置和方法中，在半导体芯片（2）和封装（1）的接合工序中，半导体芯片（2）在实际使用温度条件下保持在温度平衡状态， 点焊件（3）插入在半导体芯片（2）和封装（1）之间，电极焊盘（9）位于半导体芯片（2）的上表面和电极端子（8） 电连接到高电压电脉冲源（4）的输出端子（5）彼此并联并电连接。 随后，在高压电脉冲源（4）中产生高压电脉冲，并施加到电极焊盘（9）以熔化低熔点焊接部件（3），从而使封装（1）和 半导体颗粒（2）。 可以在半导体颗粒（2）的实际使用温度条件下进行接合处理，并且抑制对半导体颗粒（2）的热应力，并且可以提高半导体颗粒（2）的寿命。
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公开(公告)号：US4733478A
公开(公告)日：1988-03-29
申请号：US915800
申请日：1986-10-06
申请人： Takao Kamei , Fuminobu Ono , Keiichi Komai , Takeshi Wakabayashi
发明人： Takao Kamei , Fuminobu Ono , Keiichi Komai , Takeshi Wakabayashi
CPC分类号： C10F5/00
摘要： This disclosure relates to a process for steam dewatering of brown coal, using a plurality of autoclaves, each of which, in cyclic sequence among the autoclaves, repeats a batch process comprised of an atmospheric pressure stage to unload the coal dewatered and to load the coal to be dewatered, a heating stage to heat and dewater the loaded coal and a depressurizing stage to lower the interior pressure for the unloading of coal, wherein the heating stage comprises first and second steaming steps successive in this order at the final period of this stage to be supplied with fresh steam from an external source, and an initial steaming step under which the autoclave is connected with the other autoclave undergoing the second heating step, thereby intensifying the steam ventilation at the second heating step.
摘要翻译： 本公开涉及一种使用多个高压釜的蒸汽脱水褐煤的方法，每个高压釜在高压釜之间以循环顺序重复包括大气压级的分批处理，以卸载脱硫的煤和装载煤 脱水，加热阶段以对装载的煤进行加热和脱水，以及减压阶段以降低用于卸载煤的内部压力，其中加热阶段包括在该阶段的最后阶段以此顺序连续的第一和第二蒸汽步骤 从外部来源供给新鲜蒸汽，以及初始蒸汽步骤，高压釜与经历第二加热步骤的另一个高压釜连接，从而在第二加热步骤增强蒸汽通风。
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公开(公告)号：US06639452B2
公开(公告)日：2003-10-28
申请号：US10319995
申请日：2002-12-16
申请人： Fuminobu Ono , Yoshikazu Nishimura
发明人： Fuminobu Ono , Yoshikazu Nishimura
IPC分类号： G05F110
摘要： An active bias circuit having a combined configuration of the Wilson and Widlar current source configurations is provided, which makes it possible to set the output bias voltage at approximately zero (0V) even if a reference voltage applied to generate a reference current does not reach 0V. This circuit comprises cascode-connected first and second transistors, cascode-connected third and fourth transistors, and a resistor with a specific voltage drop generated by a current flowing through the same. The absolute value of the output bias voltage is decreased by the value of the voltage drop of the resistor compared with the case where the resistor is not provided. The resistor is provided between the gates/bases of the first and third transistors, or between the gate/base and source/emitter of the fourth transistor.
摘要翻译： 提供了具有Wilson和Widlar电流源配置的组合配置的主动偏置电路，这使得即使施加用于产生参考电流的参考电压没有达到0V，也可以将输出偏置电压设置在大约零（0V） 。 该电路包括共源共栅连接的第一和第二晶体管，共源共栅连接的第三和第四晶体管，以及具有由流过该晶体管的电流产生的特定电压降的电阻器。 与未设置电阻器的情况相比，输出偏置电压的绝对值减小电阻器的电压降值。 电阻器设置在第一和第三晶体管的栅极/基极之间，或第四晶体管的栅极/基极和源极/发射极之间。
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