公开(公告)号：US08108199B2

公开(公告)日：2012-01-31

申请号：US12130104

申请日：2008-05-30

申请人： Gabor Bobok ,  Wolfgang Roesner ,  Derek E. Williams

发明人： Gabor Bobok ,  Wolfgang Roesner ,  Derek E. Williams

IPC分类号： G06F9/45

CPC分类号： G06F17/5022

摘要： According to a method of simulation processing, an instrumented simulation executable model of a design is built by compiling one or more hardware description language (HDL) files specifying one or more design entities within the design and one or more instrumentation entities and instantiating instances of the one or more instrumentation entities within instances of the one or more design entities. Operation of the design is then simulated utilizing the instrumented simulation executable model. Simulating operation includes each of multiple instantiations of the one or more instrumentation entities generating a respective external phase signal representing an occurrence of a particular phase of operation and instrumentation combining logic generating from external phase signals of the multiple instantiations of the one or more instrumentation entities an aggregate phase signal representing an occurrence of the particular phase.

摘要翻译： 根据模拟处理的方法，通过编译指定设计中的一个或多个设计实体的一个或多个硬件描述语言（HDL）文件和一个或多个设备实体和一个或多个设备实例的实例化来构建设计的仪器化模拟可执行模型 在一个或多个设计实体的实例内的一个或多个仪表实体。 然后使用仪器化模拟可执行模型对设计的操作进行模拟。 模拟操作包括一个或多个仪器实体的多个实例中的每个实例，其产生表示特定操作阶段的出现的相应的外部相位信号，以及组合从一个或多个仪器实体的多个实例的外部相位信号产生的逻辑 聚合相位信号表示特定相位的出现。

公开(公告)号：US07912694B2

公开(公告)日：2011-03-22

申请号：US11668542

申请日：2007-01-30

申请人： Gabor Bobok ,  Wolfgang Roesner ,  Derek E. Williams

发明人： Gabor Bobok ,  Wolfgang Roesner ,  Derek E. Williams

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5022

摘要： According to a method of simulation processing, one or more HDL source files describing a digital design including a plurality of hierarchically arranged design entities are received. The one or more HDL source files include one or more statements instantiating a plurality of print events within the plurality of hierarchically arranged design entities, where each print event has an associated message and at least one associated signal in the digital design. The one or more HDL source files are processed to obtain a simulation executable model including a data structure describing the plurality of print events defined for the simulation executable model and associating each of the plurality of print events with its respective associated signal.

摘要翻译： 根据模拟处理的方法，接收描述包括多个分层布置的设计实体的数字设计的一个或多个HDL源文件。 一个或多个HDL源文件包括实例化多个分层布置的设计实体中的多个打印事件的一个或多个语句，其中每个打印事件具有相关联的消息和数字设计中的至少一个相关联的信号。 处理一个或多个HDL源文件以获得模拟可执行模型，其包括描述为模拟可执行模型定义的多个打印事件的数据结构，并将多个打印事件中的每一个与其相应的相关信号相关联。

公开(公告)号：US20100153083A1

公开(公告)日：2010-06-17

申请号：US12336019

申请日：2008-12-16

申请人： Gabor Bobok ,  Wolfgang Roesner ,  Derek E. Williams

发明人： Gabor Bobok ,  Wolfgang Roesner ,  Derek E. Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： In response to receiving HDL file(s) that specify a plurality of hierarchically arranged design entities defining a design to be simulated and that specify an instrumentation entity for monitoring simulated operation of the design, an instrumented simulation executable model of the design is built. Building the model includes compiling the HDL file(s) specifying the plurality of hierarchically arranged design entities defining the design and instantiating at least one instance of each of the plurality of hierarchically arranged design entities, and further includes instantiating an instance of the instrumentation entity within an instance of a particular design entity among the plurality of design entities and, based upon a reference in an instrumentation statement in the one or more HDL files, logically attaching an input of the instance of the instrumentation entity to an input source within the design that is outside the scope of the particular design entity.

摘要翻译： 响应于接收到指定多个分层布置的设计实体的定义待仿真设计的HDL文件，并指定用于监视设计的模拟操作的仪器实体，构建了该设计的仪表化仿真可执行模型。 构建模型包括编译指定定义设计的多个分层布置的设计实体的HDL文件，并且实例化多个分级排列的设计实体中的每一个的至少一个实例，并且还包括实例化所述多个分层布置设计实体内的所述检测实体的实例 所述多个设计实体中的特定设计实体的实例，并且基于所述一个或多个HDL文件中的检测语句中的引用，将所述检测实体的实例的输入逻辑地附加到所述设计中的输入源， 不在特定设计实体的范围之内。

公开(公告)号：US07493248B2

公开(公告)日：2009-02-17

申请号：US11382088

申请日：2006-05-08

申请人： Gabor Bobok ,  Wolfgang Roesner ,  Derek E. Williams

发明人： Gabor Bobok ,  Wolfgang Roesner ,  Derek E. Williams

IPC分类号： G06F9/45

CPC分类号： G06F17/5022

摘要： According to a method of simulation processing, an instrumented simulation executable model of a design is built by compiling one or more hardware description language (HDL) files specifying one or more design entities within the design and one or more instrumentation entities and instantiating instances of the one or more instrumentation entities within instances of the one or more design entities. Operation of the design is then simulated utilizing the instrumented simulation executable model. Simulating operation includes each of multiple instantiations of the one or more instrumentation entities generating a respective external phase signal representing an occurrence of a particular phase of operation and instrumentation combining logic generating from external phase signals of the multiple instantiations of the one or more instrumentation entities an aggregate phase signal representing an occurrence of the particular phase.

摘要翻译： 根据模拟处理的方法，通过编译指定设计中的一个或多个设计实体的一个或多个硬件描述语言（HDL）文件和一个或多个设备实体和一个或多个设备实例的实例化来构建设计的仪器化模拟可执行模型 在一个或多个设计实体的实例内的一个或多个仪表实体。 然后使用仪器化模拟可执行模型对设计的操作进行模拟。 模拟操作包括一个或多个仪器实体的多个实例中的每个实例，其产生表示特定操作阶段的出现的相应的外部相位信号，以及组合从一个或多个仪器实体的多个实例的外部相位信号产生的逻辑 聚合相位信号表示特定相位的出现。

公开(公告)号：US20070260441A1

公开(公告)日：2007-11-08

申请号：US11382088

申请日：2006-05-08

申请人： Gabor Bobok ,  Wolfgang Roesner ,  Derek Williams

发明人： Gabor Bobok ,  Wolfgang Roesner ,  Derek Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： According to a method of simulation processing, an instrumented simulation executable model of a design is built by compiling one or more hardware description language (HDL) files specifying one or more design entities within the design and one or more instrumentation entities and instantiating instances of the one or more instrumentation entities within instances of the one or more design entities. Operation of the design is then simulated utilizing the instrumented simulation executable model. Simulating operation includes each of multiple instantiations of the one or more instrumentation entities generating a respective external phase signal representing an occurrence of a particular phase of operation and instrumentation combining logic generating from external phase signals of the multiple instantiations of the one or more instrumentation entities an aggregate phase signal representing an occurrence of the particular phase.

摘要翻译： 根据模拟处理的方法，通过编译指定设计中的一个或多个设计实体的一个或多个硬件描述语言（HDL）文件和一个或多个设备实体和一个或多个设备实例的实例化来构建设计的仪器化模拟可执行模型 在一个或多个设计实体的实例内的一个或多个仪表实体。 然后使用仪器化模拟可执行模型对设计的操作进行模拟。 模拟操作包括一个或多个仪器实体的多个实例中的每个实例，其产生表示特定操作阶段的出现的相应的外部相位信号，以及组合从一个或多个仪器实体的多个实例的外部相位信号产生的逻辑 聚合相位信号表示特定相位的出现。

公开(公告)号：US08495533B2

公开(公告)日：2013-07-23

申请号：US11522036

申请日：2006-09-16

申请人： Gabor Drasny ,  Gabor Bobok ,  Ali El-Zein

发明人： Gabor Drasny ,  Gabor Bobok ,  Ali El-Zein

IPC分类号： G06F17/50

CPC分类号： G06F17/5054 ,  G06F17/5045

摘要： Preprocessing parallel sequences of “wait” statements and synthesizing these multiple “wait” statements to construct support for RTL tools. This is accomplished by preprocessing a VHDL process with multiple wait statements (referred to as BehFSM) into an equivalent register transfer.

摘要翻译： 预处理“等待”语句的并行序列，并合成这些多个“等待”语句来构建对RTL工具的支持。 这是通过将具有多个等待语句（称为BehFSM）的VHDL进程预处理为等效的寄存器传输来实现的。

公开(公告)号：US20080195368A1

公开(公告)日：2008-08-14

申请号：US12060717

申请日：2008-04-01

申请人： GABOR BOBOK ,  Wolfgang Roesner ,  Matyas A. Sustik ,  Derek E. Williams

发明人： GABOR BOBOK ,  Wolfgang Roesner ,  Matyas A. Sustik ,  Derek E. Williams

IPC分类号： G06G7/48

CPC分类号： G06F17/5022

摘要： According to a method of simulation processing, a simulation model is received that includes a plurality of design entity instances modeling a digital system and one or more instrumentation entity instances, separate from the plurality of design entity instances, that generate instances of instrumentation events for testing purposes during simulation. In response to receiving an exclusion list identifying at least one instance of one or more instrumentation events to be removed from the simulation model, at least one instance of the one or more instrumentation events and associated logic elements are removed from the one or more instrumentation entity instances of the simulation model prior to simulation, such that a more compact simulation model is obtained.

摘要翻译： 根据模拟处理的方法，接收模拟模型，其包括建立数字系统的多个设计实体实例和与多个设计实体实例分开的一个或多个仪表实体实例，其生成用于测试的仪表事件的实例 模拟过程中的目的。 响应于接收到排除列表，其识别要从仿真模型中移除的一个或多个仪器事件的至少一个实例，所述一个或多个检测事件和相关逻辑元件的至少一个实例从所述一个或多个检测实体中移除 在模拟之前的仿真模型的实例，使得获得更紧凑的模拟模型。

公开(公告)号：US20070260443A1

公开(公告)日：2007-11-08

申请号：US11381437

申请日：2006-05-03

申请人： Gabor Bobok ,  Wolfgang Roesner ,  Derek Williams

发明人： Gabor Bobok ,  Wolfgang Roesner ,  Derek Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： According to a method of data processing, a data set including at least one entry specifying a signal group by a predetermined signal group name is received by a data processing system. In response to receipt of the data set, the entry in the data set is processed to identify the signal group name. Signal group information associated with an event trace file containing simulation results is accessed to determine signal names of multiple signals that are members of the signal group. Simulation results from the event trace file that are associated with instances of said multiple signals are then included within a presentation of simulation results.

摘要翻译： 根据数据处理的方法，由数据处理系统接收包括由预定信号组名称指定信号组的至少一个条目的数据集。 响应于数据集的接收，处理数据集中的条目以识别信号组名称。 与包含模拟结果的事件跟踪文件相关联的信号组信息被访问以确定作为信号组成员的多个信号的信号名称。 然后将与所述多个信号的实例相关联的事件跟踪文件的仿真结果包括在仿真结果的呈现中。

公开(公告)号：US20070061121A1

公开(公告)日：2007-03-15

申请号：US11226969

申请日：2005-09-15

申请人： Gabor Bobok ,  Wolfgang Roesner ,  Matyas Sustik ,  Derek Williams

发明人： Gabor Bobok ,  Wolfgang Roesner ,  Matyas Sustik ,  Derek Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： According to a method of simulation processing, a simulation model is received that includes a plurality of design entity instances modeling a digital system and one or more instrumentation entity instances, separate from the plurality of design entity instances, that generate instances of instrumentation events for testing purposes during simulation. In response to receiving an exclusion list identifying at least one instance of one or more instrumentation events to be removed from the simulation model, at least one instance of the one or more instrumentation events and associated logic elements are removed from the one or more instrumentation entity instances of the simulation model prior to simulation, such that a more compact simulation model is obtained.

摘要翻译： 根据模拟处理的方法，接收模拟模型，其包括建立数字系统的多个设计实体实例和与多个设计实体实例分开的一个或多个仪表实体实例，其生成用于测试的仪表事件的实例 模拟过程中的目的。 响应于接收到排除列表，其识别要从仿真模型中移除的一个或多个仪器事件的至少一个实例，所述一个或多个检测事件和相关逻辑元件的至少一个实例从所述一个或多个检测实体中移除 在模拟之前的仿真模型的实例，使得获得更紧凑的模拟模型。

公开(公告)号：US20120192133A1

公开(公告)日：2012-07-26

申请号：US13436196

申请日：2012-03-30

申请人： Jason R. Baumgartner ,  Gabor Bobok ,  Paul Joseph Roessler ,  Mark Allen Williams

发明人： Jason R. Baumgartner ,  Gabor Bobok ,  Paul Joseph Roessler ,  Mark Allen Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/504 ,  G06F2217/84

摘要： A technique for verification of a retimed logic design using liveness checking includes assigning a liveness gate to a liveness property for an original netlist and assigning a fairness gate to a fairness constraint for the original netlist. In this case, the fairness gate is associated with the liveness gate and is asserted for at least one time-step during any valid behavioral loop associated with the liveness gate. The original netlist is retimed, using a retiming engine, to provide a retimed netlist. The liveness and fairness gates of the retimed netlist are retimed such that a lag of the fairness gate is no greater than a lag of the liveness gate. Verification analysis is then performed on the retimed netlist. Finally, when the verification analysis yields a valid counter-example trace for the retimed netlist, a liveness violation for the original netlist is returned.

摘要翻译： 用于使用活动检查验证重新定时逻辑设计的技术包括将活跃门分配给原始网表的活动属性，并将公平门分配给原始网表的公平约束。 在这种情况下，公平门与活跃门相关联，并且在与活跃门相关联的任何有效行为循环期间被断言至少一个时间步长。 使用重新定时引擎重新计算原始网表，以提供重新定时的网表。 重新定义的网表的活跃和公平的门被重新定位，使得公平门的滞后不大于活跃门的滞后。 然后在重新定时的网表上进行验证分析。 最后，当验证分析为重新定时的网表产生有效的对照示例时，返回原始网表的活动违反。