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    Synthesizing VHDL multiple wait behavioral FSMs into RT level FSMs by preprocessing
    1.
    发明授权
    Synthesizing VHDL multiple wait behavioral FSMs into RT level FSMs by preprocessing 失效
    通过预处理将VHDL多等待行为FSM合成到RT级FSM中

    公开(公告)号：US08495533B2

    公开(公告)日：2013-07-23

    申请号：US11522036

    申请日：2006-09-16

    申请人： Gabor Drasny ,  Gabor Bobok ,  Ali El-Zein

    发明人： Gabor Drasny ,  Gabor Bobok ,  Ali El-Zein

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5054 ,  G06F17/5045

    摘要： Preprocessing parallel sequences of “wait” statements and synthesizing these multiple “wait” statements to construct support for RTL tools. This is accomplished by preprocessing a VHDL process with multiple wait statements (referred to as BehFSM) into an equivalent register transfer.

    摘要翻译： 预处理“等待”语句的并行序列，并合成这些多个“等待”语句来构建对RTL工具的支持。 这是通过将具有多个等待语句（称为BehFSM）的VHDL进程预处理为等效的寄存器传输来实现的。

    Unrolling hardware design generate statements in a source window debugger
    2.
    发明授权
    Unrolling hardware design generate statements in a source window debugger 有权
    展开硬件设计在源窗口调试器中生成语句

    公开(公告)号：US07823097B2

    公开(公告)日：2010-10-26

    申请号：US11532216

    申请日：2006-09-15

    申请人： Gabor Drasny ,  Gabor Bobok ,  Ali El-Zein ,  Fadi Zaraket

    发明人： Gabor Drasny ,  Gabor Bobok ,  Ali El-Zein ,  Fadi Zaraket

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505 ,  G06F17/5022

    摘要： Unrolling the “generate” statement of a hardware description language (“HDL”) and displaying the unrolled HDL. For a conditional generate the condition is evaluated. If the statement is true the enclosed HDL code will be displayed. For an iterative generate, the enclosing HDL will be displayed as many times as specified by the bounds of the iteration scheme. This allows, for example, simulation value annotations for signals declared inside the generate statement, semantic navigation inside the generate statements, and allows the user to visualize what is included in the target design.

    摘要翻译： 展开硬件描述语言（“HDL”）的“生成”语句并显示展开的HDL。 对于条件生成条件进行评估。 如果声明为真，则将显示附带的HDL代码。 对于迭代生成，封闭的HDL将被显示为迭代方案边界所指定的次数。 这允许例如生成语句内声明的信号的模拟值注释，生成语句内的语义导航，并允许用户可视化目标设计中包含的内容。

    Method, system, and program product for pre-compile processing of hardware design language (HDL) source files
    3.
    发明授权
    Method, system, and program product for pre-compile processing of hardware design language (HDL) source files 失效
    方法，系统和程序产品，用于硬件设计语言（HDL）源文件的预编译处理

    公开(公告)号：US07506287B2

    公开(公告)日：2009-03-17

    申请号：US11521917

    申请日：2006-09-16

    申请人： Gabor Drasny ,  Gabor Bobok ,  Ali El-Zein ,  Fadi Zaraket ,  Hussein Sharafeddin

    发明人： Gabor Drasny ,  Gabor Bobok ,  Ali El-Zein ,  Fadi Zaraket ,  Hussein Sharafeddin

    IPC分类号： G06F17/50

    CPC分类号： G06F11/3664 ,  G06F8/447

    摘要： A method includes pre-compilation operations on HDL source code files, creating a “make it” file, on demand processing of the HDL source code in an HDL source browser, and resolving overloaded function and operator calls in an HDL source code browser debugger. Construct a list of all HDL files a list of HDL files to be processed. Send an HDL file in the list for compiling. If compilation is successful, branch to add the HDL file to an end of target file and that HDL file is removed from the list. The list is tested for remaining files and then a next file in the list is sent for compiling. After all files in the list have been processed, the HDL files which have been processed are checked for failures to compile and if any of said HDL files to be processed have failed to compile the method branches back to repeating the process until all runs are successful.

    摘要翻译： 一种方法包括对HDL源代码文件进行预编译操作，在HDL源浏览器中创建“make it”文件，按需处理HDL源代码，并在HDL源代码浏览器调试器中解析重载函数和操作符调用。 构建所有HDL文件的列表，列出要处理的HDL文件。 在列表中发送一个HDL文件进行编译。 如果编译成功，请将HDL文件添加到目标文件的末尾，并从列表中删除该HDL文件。 该列表被测试剩余的文件，然后发送列表中的下一个文件进行编译。 在处理列表中的所有文件之后，检查已处理的HDL文件，以便编译失败，并且如果要处理的所有HDL文件中的任何一个无法编译方法分支回到重复进程，直到所有运行成功 。

    Unrolling Hardware Design Generate Statements in a Source Window Debugger
    4.
    发明申请
    Unrolling Hardware Design Generate Statements in a Source Window Debugger 有权
    展开硬件设计在源窗口生成语句调试器

    公开(公告)号：US20080072206A1

    公开(公告)日：2008-03-20

    申请号：US11532216

    申请日：2006-09-15

    申请人： Gabor Drasny ,  Gabor Bobok ,  Ali El-Zein ,  Fadi Zaraket

    发明人： Gabor Drasny ,  Gabor Bobok ,  Ali El-Zein ,  Fadi Zaraket

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505 ,  G06F17/5022

    摘要： Unrolling the “generate” statement of a hardware description language (“HDL”) and displaying the unrolled HDL. For a conditional generate the condition is evaluated. If the statement is true the enclosed HDL code will be displayed. For an iterative generate, the enclosing HDL will be displayed as many times as specified by the bounds of the iteration scheme. This allows, for example, simulation value annotations for signals declared inside the generate statement, semantic navigation inside the generate statements, and allows the user to visualize what is included in the target design.

    摘要翻译： 展开硬件描述语言（“HDL”）的“生成”语句并显示展开的HDL。 对于条件生成条件进行评估。 如果声明为真，则将显示附带的HDL代码。 对于迭代生成，封闭的HDL将被显示为迭代方案边界所指定的次数。 这允许例如生成语句内声明的信号的模拟值注释，生成语句内的语义导航，并允许用户可视化目标设计中包含的内容。

    Compiler option consistency checking during incremental hardware design language compilation
    5.
    发明授权
    Compiler option consistency checking during incremental hardware design language compilation 失效
    增量硬件设计语言编译期间的编译器选项一致性检查

    公开(公告)号：US08230406B2

    公开(公告)日：2012-07-24

    申请号：US11530495

    申请日：2006-09-11

    申请人： Richard L. H. Carbone ,  Gabor Bobok ,  Gabor Drasny ,  Ali El-Zein

    发明人： Richard L. H. Carbone ,  Gabor Bobok ,  Gabor Drasny ,  Ali El-Zein

    IPC分类号： G06F9/45

    CPC分类号： G06F17/505 ,  G06F8/48

    摘要： Method, system, and program product for processing hardware design language code to facilitate reuse of compiled code units including options and option values in compiled code units. The method includes the steps of grouping options and option values to determine if code controlled by them will be reused; and determining options and option values that would permit and prevent reuse of compiled code units.

    摘要翻译： 用于处理硬件设计语言代码的方法，系统和程序产品，以便于编译代码单元的重用，包括编译代码单元中的选项和选项值。 该方法包括对选项和选项值进行分组以确定由其控制的代码是否将被重用的步骤; 并确定允许和防止重用已编译代码单元的选项和选项值。

    Compiler Option Consistency Checking During Incremental Hardware Design Language Compilation
    6.
    发明申请
    Compiler Option Consistency Checking During Incremental Hardware Design Language Compilation 失效
    增量硬件设计语言编译期间的编译器选项一致性检查

    公开(公告)号：US20080127130A1

    公开(公告)日：2008-05-29

    申请号：US11530495

    申请日：2006-09-11

    申请人： Richard L.H. Carbone ,  Gabor Bobok ,  Gabor Drasny ,  Ali El-Zein

    发明人： Richard L.H. Carbone ,  Gabor Bobok ,  Gabor Drasny ,  Ali El-Zein

    IPC分类号： G06F9/45

    CPC分类号： G06F17/505 ,  G06F8/48

    摘要： Method, system, and program product for processing hardware design language code to facilitate reuse of compiled code units including options and option values in compiled code units. The method includes the steps of grouping options and option values to determine if code controlled by them will be reused; and determining options and option values that would permit and prevent reuse of compiled code units.

    摘要翻译： 用于处理硬件设计语言代码的方法，系统和程序产品，以便于编译代码单元的重用，包括编译代码单元中的选项和选项值。 该方法包括对选项和选项值进行分组以确定由其控制的代码是否将被重用的步骤; 并确定允许和防止重用已编译代码单元的选项和选项值。

    Synthesizing VHDL multiple wait behavioral FSMs into RT level FSMs by preprocessing
    7.
    发明申请
    Synthesizing VHDL multiple wait behavioral FSMs into RT level FSMs by preprocessing 失效
    通过预处理将VHDL多等待行为FSM合成到RT级FSM中

    公开(公告)号：US20080127126A1

    公开(公告)日：2008-05-29

    申请号：US11522036

    申请日：2006-09-16

    申请人： Gabor Drasny ,  Gabor Bobok ,  Ali El-Zein

    发明人： Gabor Drasny ,  Gabor Bobok ,  Ali El-Zein

    IPC分类号： G06F9/45

    CPC分类号： G06F17/5054 ,  G06F17/5045

    摘要： Preprocessing parallel sequences of “wait” statements and synthesizing these multiple “wait” statements to construct support for RTL tools. This is accomplished by preprocessing a VHDL process with multiple wait statements (referred to as BehFSM) into an equivalent register transfer

    摘要翻译： 预处理“等待”语句的并行序列，并合成这些多个“等待”语句来构建对RTL工具的支持。 这是通过将具有多个等待语句（称为BehFSM）的VHDL进程预处理为等效的寄存器传输来实现的

    METHOD, SYSTEM AND PROGRAM PRODUCT SUPPORTING SPECIFICATION OF SIGNALS FOR SIMULATION RESULT VIEWING
    9.
    发明申请
    METHOD, SYSTEM AND PROGRAM PRODUCT SUPPORTING SPECIFICATION OF SIGNALS FOR SIMULATION RESULT VIEWING 失效
    方法，系统和程序产品支持模拟结果查看信号的规范

    公开(公告)号：US20070260443A1

    公开(公告)日：2007-11-08

    申请号：US11381437

    申请日：2006-05-03

    申请人： Gabor Bobok ,  Wolfgang Roesner ,  Derek Williams

    发明人： Gabor Bobok ,  Wolfgang Roesner ,  Derek Williams

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5022

    摘要： According to a method of data processing, a data set including at least one entry specifying a signal group by a predetermined signal group name is received by a data processing system. In response to receipt of the data set, the entry in the data set is processed to identify the signal group name. Signal group information associated with an event trace file containing simulation results is accessed to determine signal names of multiple signals that are members of the signal group. Simulation results from the event trace file that are associated with instances of said multiple signals are then included within a presentation of simulation results.

    摘要翻译： 根据数据处理的方法，由数据处理系统接收包括由预定信号组名称指定信号组的至少一个条目的数据集。 响应于数据集的接收，处理数据集中的条目以识别信号组名称。 与包含模拟结果的事件跟踪文件相关联的信号组信息被访问以确定作为信号组成员的多个信号的信号名称。 然后将与所述多个信号的实例相关联的事件跟踪文件的仿真结果包括在仿真结果的呈现中。

    Method, system and program product for selectively removing instrumentation logic from a simulation model
    10.
    发明申请
    Method, system and program product for selectively removing instrumentation logic from a simulation model 失效
    用于从仿真模型中选择性地移除仪表逻辑的方法，系统和程序产品

    公开(公告)号：US20070061121A1

    公开(公告)日：2007-03-15

    申请号：US11226969

    申请日：2005-09-15

    申请人： Gabor Bobok ,  Wolfgang Roesner ,  Matyas Sustik ,  Derek Williams

    发明人： Gabor Bobok ,  Wolfgang Roesner ,  Matyas Sustik ,  Derek Williams

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5022

    摘要： According to a method of simulation processing, a simulation model is received that includes a plurality of design entity instances modeling a digital system and one or more instrumentation entity instances, separate from the plurality of design entity instances, that generate instances of instrumentation events for testing purposes during simulation. In response to receiving an exclusion list identifying at least one instance of one or more instrumentation events to be removed from the simulation model, at least one instance of the one or more instrumentation events and associated logic elements are removed from the one or more instrumentation entity instances of the simulation model prior to simulation, such that a more compact simulation model is obtained.

    摘要翻译： 根据模拟处理的方法，接收模拟模型，其包括建立数字系统的多个设计实体实例和与多个设计实体实例分开的一个或多个仪表实体实例，其生成用于测试的仪表事件的实例 模拟过程中的目的。 响应于接收到排除列表，其识别要从仿真模型中移除的一个或多个仪器事件的至少一个实例，所述一个或多个检测事件和相关逻辑元件的至少一个实例从所述一个或多个检测实体中移除 在模拟之前的仿真模型的实例，使得获得更紧凑的模拟模型。